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Review request for Default.


Repository: gem5


Description
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Changeset 11648:c2eff34bfbcd
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riscv: [Patch 2/5] Added RISC-V multiply extension RV64M

Second of five patches adding RISC-V to GEM5.  This patch adds the
RV64M extension, which includes integer multiply and divide instructions.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I.

Patch 3 will implement the floating point extensions, RV64FD; patch 4 will
implement the atomic memory instructions, RV64A; and patch 5 will add
support for timing, minor, and detailed CPU models that is missing from
the first four patches.

Signed-off by: Alec Roelke


Diffs
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  src/arch/riscv/isa/decoder.isa PRE-CREATION 

Diff: http://reviews.gem5.org/r/3627/diff/


Testing
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Thanks,

Alec Roelke

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