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Ship it! Ship It! - Tony Gutierrez On Sept. 29, 2016, 11:59 a.m., Alec Roelke wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3627/ > ----------------------------------------------------------- > > (Updated Sept. 29, 2016, 11:59 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11656:8fa017d0d977 > --------------------------- > riscv: [Patch 2/5] Added RISC-V multiply extension RV64M > > Second of five patches adding RISC-V to GEM5. This patch adds the > RV64M extension, which includes integer multiply and divide instructions. > > Patch 1 introduced RISC-V and implemented the base instruction set, RV64I. > > Patch 3 will implement the floating point extensions, RV64FD; patch 4 will > implement the atomic memory instructions, RV64A; and patch 5 will add > support for timing, minor, and detailed CPU models that is missing from > the first four patches. > > [Added mulw instruction that was missed when dividing changes among > patches.] > Signed-off by: Alec Roelke > > > Diffs > ----- > > src/arch/riscv/isa/decoder.isa PRE-CREATION > > Diff: http://reviews.gem5.org/r/3627/diff/ > > > Testing > ------- > > > Thanks, > > Alec Roelke > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
