Hello all, I'd like to know if the following patch may interest the community.
I split conditionally executed AArch64 instructions into two or three uops, in order to use at most 3 register file ports, instead of 4 in the current code. The vast majority if not all AArch64 uops use up to 3 RF ports. More specifically: CSEL (and similarly CSINC, CSINV, CSNEG FCSEL) are split as follows: CSEL Rd, Rn, Rm, cond uop 1: (cond) ? Tmp0 = Rn : 0 uop 2: (!cond) ? Tmp1 = Rm : 0 uop 3: Rd = Tmp0 + Tmp1 CCMN (and similarly CCMP, FCCMP) are split as: CCMP Rn, Rm, #imm, cond uop 1: Tmp_nzcv = CMP Rn, Rm uop 2: (cond) ? nzcv = Tmp_nzcv : #imm Just asking because the patch works in my branch, I didn't rebase/test over gem5 mainstream. Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev