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Ship it! Ship It! - Andreas Sandberg On Oct. 14, 2016, 3:31 p.m., Bjoern A. Zeeb wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3667/ > ----------------------------------------------------------- > > (Updated Oct. 14, 2016, 3:31 p.m.) > > > Review request for Default and Andreas Sandberg. > > > Repository: gem5 > > > Description > ------- > > Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not > implmemented. With that an operating system relying on the cache line sizes > reported in order to manage the caches would (a) panic given the returned > value 0 is not valid (high bit is RES1) or (b) worst case would assume a > cache line size of 4 doing a tremendous amount of extra instruction work > (including fetching). Return the same values as for ARMv7 as the fields seem > to be the same, or RES0/1 seem to be reported accordingly for AArch64 > > In collaboration with: Andrew Turner > > > Diffs > ----- > > src/arch/arm/isa.cc 9c7b55faea5d > > Diff: http://reviews.gem5.org/r/3667/diff/ > > > Testing > ------- > > Checked on FreeBSD boots with extra printfs; also observed a reduction of a > factor of about 10 in instruction fetches for a simple micro-test. > > > Thanks, > > Bjoern A. Zeeb > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
