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(Updated Oct. 24, 2016, 2:56 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 11688:9dba209f1590 --------------------------- mem: Split the hit_latency into tag_latency and data_latency If the cache access mode is parallel, i.e. "sequential_access" parameter is set to "False", tags and data are accessed in parallel. Therefore, the hit_latency is the maximum latency between tag_latency and data_latency. On the other hand, if the cache access mode is sequential, i.e. "sequential_access" parameter is set to "True", tags and data are accessed sequentially. Therefore, the hit_latency is the sum of tag_latency plus data_latency. Diffs (updated) ----- src/mem/cache/tags/base.cc 4aac82f10951 src/mem/cache/tags/base_set_assoc.hh 4aac82f10951 src/mem/cache/tags/fa_lru.cc 4aac82f10951 configs/common/Caches.py 4aac82f10951 configs/common/O3_ARM_v7a.py 4aac82f10951 configs/example/arm/devices.py 4aac82f10951 configs/learning_gem5/part1/caches.py 4aac82f10951 src/mem/cache/Cache.py 4aac82f10951 src/mem/cache/base.hh 4aac82f10951 src/mem/cache/base.cc 4aac82f10951 src/mem/cache/tags/Tags.py 4aac82f10951 src/mem/cache/tags/base.hh 4aac82f10951 Diff: http://reviews.gem5.org/r/3502/diff/ Testing ------- Tested using --Debug-flags=Cache Thanks, Sophiane SENNI _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
