> On Nov. 10, 2016, 4:37 p.m., Tony Gutierrez wrote: > > src/arch/riscv/locked_mem.hh, line 96 > > <http://reviews.gem5.org/r/3693/diff/1/?file=63027#file63027line96> > > > > Should you be using cacheBlockMask here, as opposed to 0xF?
That would make more sense to me, also, but cacheBlockMask isn't a parameter for handleLockedRead. In MIPS, which this is based off of, ~0xF is used here as well (and in handleLockedWrite even though handleLockedWrite *does* have a cacheBlockMask parameter). - Alec ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3693/#review9030 ----------------------------------------------------------- On Nov. 2, 2016, 7:34 p.m., Alec Roelke wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3693/ > ----------------------------------------------------------- > > (Updated Nov. 2, 2016, 7:34 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11694:1c3068cb5c86 > --------------------------- > riscv: [Patch 7/5] Corrected LRSC semantics > > RISC-V makes use of load-reserved and store-conditional instructions to > enable creation of lock-free concurrent data manipulation as well as > ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO > instructions (the latter of which do not follow LR/SC semantics). This > patch is a correction to patch 4, which added these instructions to the > implementation of RISC-V. It modifies locked_mem.hh and the > implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5 > flags and return the proper values. > > An important difference between gem5's LLSC semantics and RISC-V's LR/SC > ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to > indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V > uses 0 to indicate success and nonzero to indicate failure where the > value would indicate the error, but currently only 1 is reserved as a > failure code by the ISA reference. > > This is the seventh patch in the series which originally consisted of five > patches that added the RISC-V ISA to gem5. The original five patches added > all of the instructions and added support for more detailed CPU models and > the sixth patch corrected the implementations of Linux constants and > structs. There will be an eighth patch that adds some regression tests > for the instructions. > > Signed-off by: Alec Roelke > > > Diffs > ----- > > src/arch/riscv/isa/decoder.isa PRE-CREATION > src/arch/riscv/isa/formats/mem.isa PRE-CREATION > src/arch/riscv/locked_mem.hh PRE-CREATION > > Diff: http://reviews.gem5.org/r/3693/diff/ > > > Testing > ------- > > > Thanks, > > Alec Roelke > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
