changeset 3102db8903f5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3102db8903f5
description:
mem: Ensure InvalidateReq is considered isForward by MSHRs
This patch fixes an issue where an MSHR would incorrectly be perceived
to provide data to targets arriving after an InvalidateReq. To address
this the InvalidateReq is now treated as isForward, much like an
UpgradeReq that did not hit in the cache.
Change-Id: Ia878444d949539b5c33fd19f3e12b0b8a872275e
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelho...@arm.com>
diffstat:
src/mem/cache/cache.cc | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diffs (23 lines):
diff -r 5d33c6972dda -r 3102db8903f5 src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc Mon Dec 05 16:48:21 2016 -0500
+++ b/src/mem/cache/cache.cc Mon Dec 05 16:48:23 2016 -0500
@@ -909,7 +909,8 @@
bool blkValid = blk && blk->isValid();
if (cpu_pkt->req->isUncacheable() ||
- (!blkValid && cpu_pkt->isUpgrade())) {
+ (!blkValid && cpu_pkt->isUpgrade()) ||
+ cpu_pkt->cmd == MemCmd::InvalidateReq) {
// uncacheable requests and upgrades from upper-level caches
// that missed completely just go through as is
return nullptr;
@@ -936,8 +937,7 @@
// where the determination the StoreCond fails is delayed due to
// all caches not being on the same local bus.
cmd = MemCmd::SCUpgradeFailReq;
- } else if (cpu_pkt->cmd == MemCmd::WriteLineReq ||
- cpu_pkt->cmd == MemCmd::InvalidateReq) {
+ } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
// forward as invalidate to all other caches, this gives us
// the line in Exclusive state, and invalidates all other
// copies
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