changeset 3b2cb95f48ed in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=3b2cb95f48ed
description:
mem: Allow non invalidating snoops on an InvalidateReq MSHR
This patch changes an assertion that previously assumed that a non
invalidating snoop request should never be serviced by an
InvalidateReq MSHR. The MSHR serves as the ordering point for the
snooping packet. When the InvalidateResp reaches the cache the
snooping packet snoops the caches above to find the requested
block. One or more of the caches above will have the block since
earlier it has seen a WriteLineReq.
Change-Id: I0c147c8b5d5019e18bd34adf9af0fccfe431ae07
Reviewed-by: Andreas Hansson <andreas.hans...@arm.com>
diffstat:
src/mem/cache/cache.cc | 13 ++++++++++++-
1 files changed, 12 insertions(+), 1 deletions(-)
diffs (23 lines):
diff -r 55bd32c72867 -r 3b2cb95f48ed src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc Mon Dec 05 16:48:26 2016 -0500
+++ b/src/mem/cache/cache.cc Mon Dec 05 16:48:27 2016 -0500
@@ -1437,7 +1437,18 @@
assert(!is_error);
// response to snoop request
DPRINTF(Cache, "processing deferred snoop...\n");
- assert(!(is_invalidate && !mshr->hasPostInvalidate()));
+ // If the response is invalidating, a snooping target can
+ // be satisfied if it is also invalidating. If the reponse is, not
+ // only invalidating, but more specifically an InvalidateResp, the
+ // MSHR was created due to an InvalidateReq and a cache above is
+ // waiting to satisfy a WriteLineReq. In this case even an
+ // non-invalidating snoop is added as a target here since this is
+ // the ordering point. When the InvalidateResp reaches this cache,
+ // the snooping target will snoop further the cache above with the
+ // WriteLineReq.
+ assert(!(is_invalidate &&
+ pkt->cmd != MemCmd::InvalidateResp &&
+ !mshr->hasPostInvalidate()));
handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
break;
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev
