> On Jan. 20, 2017, 9:11 a.m., Tony Gutierrez wrote: > > LGTM, nice implementation. I just have an ask for a few more comments. > > > > 1) A high-level description of the API, and some direction on usage for > > this library would be useful as a top-level comment in the file. > > 2) LaneData view is lacking any comments. > > 3) How should users handle vector operations, e.g. multiplication? Should > > everything be handled through the views such that the primitive data types > > are accessed and normal operators used? Or should operators be overloaded > > here? > > Rekai Gonzalez Alberquilla wrote: > I will make sure the documentation is more comprehensive. > In the particular for 3), the designer inside me tells me that the > proposed class should be just the container for the bits, and provide > facilities to access bits, or parts of them, and it is up to the ISA to give > semantics to that. Therefore, operators should not be overloaded, and it is > up to the ISA side to use the data apropriately. By this I mean, the VecReg > should understand things like "Think of the bits as a vector of 32bit > elements, and give me the 3rd", but it should be agnostic of whether those > bits are a signed int, an unsigned int, a float or any other thing. > > Thanks for taking the time!
Makes sense. Thanks. - Tony ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3757/#review9292 ----------------------------------------------------------- On Jan. 16, 2017, 3:54 a.m., Rekai Gonzalez Alberquilla wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3757/ > ----------------------------------------------------------- > > (Updated Jan. 16, 2017, 3:54 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 11762:8b0fdbea39bf > --------------------------- > arch: added generic vector register > > This commit adds a new generic vector register to have a cleaner > implementation of SIMD ISAs. > > Nathanael's idea, Rekai's implementation. > > Change-Id: I60b250bba6423153b7e04d2e6988d517a70a3e6b > Reviewed-by: Andreas Sandberg <[email protected]> > > > Diffs > ----- > > src/arch/generic/vec_reg.hh PRE-CREATION > > Diff: http://reviews.gem5.org/r/3757/diff/ > > > Testing > ------- > > Builtin regressions > > > Thanks, > > Rekai Gonzalez Alberquilla > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
