changeset 9018cadf6c87 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9018cadf6c87
description:
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.
This patch:
* Introduce transactor modules that represent the gem5 ports in the
* SystemC world.
* Update the SimControl module and let it keep track of the gem5 ports.
Reviewed at http://reviews.gem5.org/r/3775/
Signed-off-by: Jason Lowe-Power <[email protected]>
diffstat:
util/tlm/examples/master_port/main.cc | 24 +++-------
util/tlm/examples/master_port/tlm.py | 2 +-
util/tlm/examples/slave_port/main.cc | 27 ++++--------
util/tlm/examples/slave_port/run_gem5.sh | 2 +-
util/tlm/examples/slave_port/tlm.py | 2 +-
util/tlm/master_transactor.cc | 62 ++++++++++++++++++++++++++++
util/tlm/master_transactor.hh | 70 ++++++++++++++++++++++++++++++++
util/tlm/sc_master_port.cc | 61 ++++++++++++++-------------
util/tlm/sc_master_port.hh | 32 ++++++++++---
util/tlm/sc_slave_port.cc | 55 ++++++++++++------------
util/tlm/sc_slave_port.hh | 30 ++++++++++---
util/tlm/sim_control.cc | 53 ++++++++++++++++++++++-
util/tlm/sim_control.hh | 17 ++++++-
util/tlm/sim_control_if.hh | 56 +++++++++++++++++++++++++
util/tlm/slave_transactor.cc | 62 ++++++++++++++++++++++++++++
util/tlm/slave_transactor.hh | 70 ++++++++++++++++++++++++++++++++
16 files changed, 510 insertions(+), 115 deletions(-)
diffs (truncated from 1003 to 300 lines):
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/master_port/main.cc
--- a/util/tlm/examples/master_port/main.cc Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/master_port/main.cc Thu Feb 09 19:15:41 2017 -0500
@@ -36,8 +36,8 @@
#include <tlm>
#include "cli_parser.hh"
+#include "master_transactor.hh"
#include "report_handler.hh"
-#include "sc_master_port.hh"
#include "sim_control.hh"
#include "stats.hh"
#include "traffic_generator.hh"
@@ -50,24 +50,16 @@
sc_core::sc_report_handler::set_handler(reportHandler);
- Gem5SystemC::Gem5SimControl simControl("gem5",
- parser.getConfigFile(),
- parser.getSimulationEnd(),
- parser.getDebugFlags());
+ Gem5SystemC::Gem5SimControl sim_control("gem5",
+ parser.getConfigFile(),
+ parser.getSimulationEnd(),
+ parser.getDebugFlags());
TrafficGenerator trafficGenerator("traffic_generator");
+ Gem5SystemC::Gem5MasterTransactor transactor("transactor", "transactor");
- tlm::tlm_target_socket<>* mem_port =
- dynamic_cast<tlm::tlm_target_socket<>*>(
- sc_core::sc_find_object("gem5.memory"));
-
- if (mem_port) {
- SC_REPORT_INFO("sc_main", "Port Found");
- trafficGenerator.socket.bind(*mem_port);
- } else {
- SC_REPORT_FATAL("sc_main", "Port Not Found");
- std::exit(EXIT_FAILURE);
- }
+ trafficGenerator.socket.bind(transactor.socket);
+ transactor.sim_control.bind(sim_control);
SC_REPORT_INFO("sc_main", "Start of Simulation");
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/master_port/tlm.py
--- a/util/tlm/examples/master_port/tlm.py Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/master_port/tlm.py Thu Feb 09 19:15:41 2017 -0500
@@ -61,7 +61,7 @@
# Create a external TLM port:
system.tlm = ExternalMaster()
system.tlm.port_type = "tlm_master"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"
# Route the connections:
system.system_port = system.membus.slave
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/slave_port/main.cc
--- a/util/tlm/examples/slave_port/main.cc Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/slave_port/main.cc Thu Feb 09 19:15:41 2017 -0500
@@ -50,6 +50,7 @@
#include "report_handler.hh"
#include "sc_target.hh"
#include "sim_control.hh"
+#include "slave_transactor.hh"
#include "stats.hh"
int
@@ -60,31 +61,21 @@
sc_core::sc_report_handler::set_handler(reportHandler);
- Gem5SystemC::Gem5SimControl simControl("gem5",
+ Gem5SystemC::Gem5SimControl sim_control("gem5",
parser.getConfigFile(),
parser.getSimulationEnd(),
parser.getDebugFlags());
- Target *memory;
unsigned long long int memorySize = 512*1024*1024ULL;
- tlm::tlm_initiator_socket <> *mem_port =
- dynamic_cast<tlm::tlm_initiator_socket<> *>(
- sc_core::sc_find_object("gem5.memory")
- );
+ Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
+ Target memory("memory",
+ parser.getVerboseFlag(),
+ memorySize,
+ parser.getMemoryOffset());
- if (mem_port) {
- SC_REPORT_INFO("sc_main", "Port Found");
- memory = new Target("memory",
- parser.getVerboseFlag(),
- memorySize,
- parser.getMemoryOffset());
-
- memory->socket.bind(*mem_port);
- } else {
- SC_REPORT_FATAL("sc_main", "Port Not Found");
- std::exit(EXIT_FAILURE);
- }
+ memory.socket.bind(transactor.socket);
+ transactor.sim_control.bind(sim_control);
SC_REPORT_INFO("sc_main", "Start of Simulation");
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/slave_port/run_gem5.sh
--- a/util/tlm/examples/slave_port/run_gem5.sh Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/slave_port/run_gem5.sh Thu Feb 09 19:15:41 2017 -0500
@@ -37,7 +37,7 @@
echo -e "\n${BGre}Create gem5 Configuration${RCol}\n"
../../../../build/ARM/gem5.opt ../../../../configs/example/fs.py \
---tlm-memory=memory \
+--tlm-memory=transactor \
--cpu-type=timing \
--num-cpu=1 \
--mem-type=SimpleMemory \
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/examples/slave_port/tlm.py
--- a/util/tlm/examples/slave_port/tlm.py Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/examples/slave_port/tlm.py Thu Feb 09 19:15:41 2017 -0500
@@ -64,7 +64,7 @@
system.tlm = ExternalSlave()
system.tlm.addr_ranges = [AddrRange('512MB')]
system.tlm.port_type = "tlm_slave"
-system.tlm.port_data = "memory"
+system.tlm.port_data = "transactor"
# Route the connections:
system.cpu.port = system.membus.slave
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/master_transactor.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/master_transactor.cc Thu Feb 09 19:15:41 2017 -0500
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#include "master_transactor.hh"
+#include "sc_master_port.hh"
+#include "sim_control.hh"
+
+namespace Gem5SystemC
+{
+
+Gem5MasterTransactor::Gem5MasterTransactor(sc_core::sc_module_name name,
+ const std::string& portName)
+ : sc_core::sc_module(name),
+ socket(portName.c_str()),
+ sim_control("sim_control"),
+ portName(portName)
+{
+ if (portName.empty()) {
+ SC_REPORT_ERROR(name, "No port name specified!\n");
+ }
+}
+
+void
+Gem5MasterTransactor::before_end_of_elaboration()
+{
+ auto* port = sim_control->getMasterPort(portName);
+
+ port->bindToTransactor(this);
+}
+
+}
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/master_transactor.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/master_transactor.hh Thu Feb 09 19:15:41 2017 -0500
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Christian Menard
+ */
+
+#ifndef __GEM5_MASTER_TRANSACTOR_HH__
+#define __GEM5_MASTER_TRANSACTOR_HH__
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <systemc>
+#include <tlm>
+
+#include "sc_master_port.hh"
+#include "sim_control_if.hh"
+
+namespace Gem5SystemC
+{
+
+class Gem5MasterTransactor : public sc_core::sc_module
+{
+ public:
+ // module interface
+ tlm_utils::simple_target_socket<SCMasterPort> socket;
+ sc_core::sc_port<Gem5SimControlInterface> sim_control;
+
+ private:
+ std::string portName;
+
+ public:
+ SC_HAS_PROCESS(Gem5MasterTransactor);
+
+ Gem5MasterTransactor(sc_core::sc_module_name name,
+ const std::string& portName);
+
+ void before_end_of_elaboration();
+};
+
+}
+
+#endif
diff -r 39b0a51c9e76 -r 9018cadf6c87 util/tlm/sc_master_port.cc
--- a/util/tlm/sc_master_port.cc Thu Feb 09 19:15:38 2017 -0500
+++ b/util/tlm/sc_master_port.cc Thu Feb 09 19:15:41 2017 -0500
@@ -34,6 +34,7 @@
#include <sstream>
+#include "master_transactor.hh"
#include "params/ExternalMaster.hh"
#include "sc_master_port.hh"
#include "sim/system.hh"
@@ -81,18 +82,26 @@
SCMasterPort::SCMasterPort(const std::string& name_,
const std::string& systemc_name,
ExternalMaster& owner_,
- Module& module)
+ Gem5SimControl& simControl)
: ExternalMaster::Port(name_, owner_),
- tSocket(systemc_name.c_str()),
peq(this, &SCMasterPort::peq_cb),
waitForRetry(false),
pendingRequest(nullptr),
needToSendRetry(false),
responseInProgress(false),
- module(module)
+ transactor(nullptr),
+ simControl(simControl)
{
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