Hello Everyone, I'm trying to debug RISC-V running on the O3 model, and I've encountered a problem where the CPU tries to speculatively execute a load instruction (which is actually along a branch that ends up not being taken) in which the data crosses a page boundary and causes a fault.
The specific section of code looks like this: ... ret ld s1,0(a1) ... If you're not familiar with RISC-V, ret is a pseudo-instruction that just jumps to whatever address is stored in the return-address register, and ld loads a 64-bit value from memory. The problem I'm encountering is that the value stored in register a1 is not a valid address as that instruction is not supposed to be executed, and it just so happens that the word it points to crosses a page boundary. When gem5 speculatively executes this, it crashes. How can I prevent gem5 from doing this? I know I could flag load and store instructions as being nonspeculative, but that will slow down execution and affect output stats. I'm working on top of these four patches: - https://gem5-review.googlesource.com/c/2304/ - https://gem5-review.googlesource.com/c/2305/5 - https://gem5-review.googlesource.com/c/2340/2 - https://gem5-review.googlesource.com/c/2341/2 Thanks, Alec Roelke _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
