[gem5-dev] Change in public/gem5[master]: riscv: fix error on memory op address overflow

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/2345

Change subject: riscv: fix error on memory op address overflow
......................................................................

riscv: fix error on memory op address overflow

Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and
gem5 would crash.  This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen.  Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.

Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 3 insertions(+), 0 deletions(-)



diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..52d7740 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,9 @@
     if (FullSystem)
         panic("translateData not implemented in RISC-V.\n");

+    if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+        return Fault(new GenericPageTableFault(req->getVaddr()));
+
     Process * p = tc->getProcessPtr();

     Fault fault = p->pTable->translate(req);

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
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