Alec Roelke has uploaded a new patch set (#6). (
https://gem5-review.googlesource.com/2345 )
Change subject: riscv: fix error on memory op address overflow
......................................................................
riscv: fix error on memory op address overflow
Previously, if a memory operation referenced an address that caused the
data to wrap around to the beginning of the memory (such as -1 or
0xFFFFFFFFFFFFFFFF), an assert would fail during address translation and
gem5 would crash. This patch fixes that by checking for such a case in
RISC-V's TLB code and returning a fault from translateData if that would
happen. Because RISC-V does support unaligned memory accesses, no
checking is performed to make sure that an access doesn't cross a cache
line.
[Update creation of page table fault to use make_shared.]
[Add comment explaining the change and assertion that the memory request
isn't zero size.]
Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
---
M src/arch/riscv/tlb.cc
1 file changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 841be24..c47260e 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -303,6 +303,17 @@
if (FullSystem)
panic("translateData not implemented in RISC-V.\n");
+ // In the O3 CPU model, sometimes a memory access will be speculatively
+ // executed along a branch that will end up not being taken where the
+ // address is invalid. In that case, return a fault rather than trying
+ // to translate it (which will cause a panic). Since RISC-V allows
+ // unaligned memory accesses, this should only happen if the request's
+ // length is long enough to wrap around from the end of the memory to
the
+ // start.
+ assert(req->getSize() > 0);
+ if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
+ return make_shared<GenericPageTableFault>(req->getVaddr());
+
Process * p = tc->getProcessPtr();
Fault fault = p->pTable->translate(req);
--
To view, visit https://gem5-review.googlesource.com/2345
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7b8ef9a5838f30184dbdbd0c7c1655e1c04a9410
Gerrit-Change-Number: 2345
Gerrit-PatchSet: 6
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
Gerrit-Reviewer: Alec Roelke <ar...@virginia.edu>
Gerrit-Reviewer: Brandon Potter <brandon.pot...@amd.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
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