Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/2963
to review the following change.
Change subject: kvm, arm: Fix incorrect PSTATE sync
......................................................................
kvm, arm: Fix incorrect PSTATE sync
The state transfer code wasn't reading back PSTATE correctly from the
CPU prior to updating the thread context and was incorreclty writing
the register as a 32-bit value when updating KVM. Correctly read back
the state before updating gem5's view of PSTATE and cast the value to
a uint64_t.
Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
---
M src/arch/arm/kvm/armv8_cpu.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 48bcc5f..08ce534 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -223,7 +223,7 @@
cpsr.ge = 0;
}
DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
- setOneReg(INT_REG(regs.pstate), cpsr);
+ setOneReg(INT_REG(regs.pstate), (uint64_t)cpsr);
for (const auto &ri : miscRegMap) {
const uint64_t value(tc->readMiscReg(ri.idx));
@@ -269,7 +269,7 @@
DPRINTF(KvmContext, "In updateThreadContext():\n");
// Update pstate thread context
- const CPSR cpsr(tc->readMiscRegNoEffect(MISCREG_CPSR));
+ const CPSR cpsr(getOneRegU64(INT_REG(regs.pstate)));
DPRINTF(KvmContext, " %s := 0x%x\n", "PSTATE", cpsr);
tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr);
tc->setCCReg(CCREG_NZ, cpsr.nz);
--
To view, visit https://gem5-review.googlesource.com/2963
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0a6ff5b77b897c756b20a20f65c420f42386360f
Gerrit-Change-Number: 2963
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
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