Hello Nikos Nikoleris,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/2964
to review the following change.
Change subject: arm: Add support for memory-mapped m5ops
......................................................................
arm: Add support for memory-mapped m5ops
Add support for a memory mapped m5op interface. When enabled, the TLB
intercepts accesses in the 64KiB region designated by the
ArmTLB.m5ops_base parameter. An access to this range maps to a
specific m5op call. The upper 8 bits of the offset into the range
denote the m5op function to call and the lower 8 bits denote the
subfunction.
Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2
Signed-off-by: Andreas Sandberg <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/ArmTLB.py
M src/arch/arm/system.cc
M src/arch/arm/system.hh
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
6 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 9100db0..dcd035c 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -75,6 +75,10 @@
have_large_asid_64 = Param.Bool(False,
"True if ASID is 16 bits in AArch64 (ARMv8)")
+ m5ops_base = Param.Addr(0,
+ "Base of the 64KiB PA range used for memory-mapped m5ops. Set to
0 "
+ "to disable.")
+
class GenericArmSystem(ArmSystem):
type = 'GenericArmSystem'
cxx_header = "arch/arm/system.hh"
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 4e6c69f..b3f711d 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -63,6 +63,7 @@
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
cxx_header = "arch/arm/tlb.hh"
+ sys = Param.System(Parent.any, "system object parameter")
size = Param.Int(64, "TLB size")
walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker")
is_stage2 = Param.Bool(False, "Is this a stage 2 TLB?")
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 322f686..50d0af9 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -65,6 +65,9 @@
_resetAddr64(p->reset_addr_64),
_physAddrRange64(p->phys_addr_range_64),
_haveLargeAsid64(p->have_large_asid_64),
+ _m5opRange(p->m5ops_base ?
+ RangeSize(p->m5ops_base, 0x10000) :
+ AddrRange(1, 0)), // Create an empty range if disabled
multiProc(p->multi_proc)
{
// Check if the physical address range is valid
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index ee286d2..9776933 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -116,6 +116,12 @@
*/
const bool _haveLargeAsid64;
+ /**
+ * Range for memory-mapped m5 pseudo ops. The range will be
+ * invalid/empty if disabled.
+ */
+ const AddrRange _m5opRange;
+
protected:
/**
* Get a boot loader that matches the kernel.
@@ -216,6 +222,12 @@
return mask(physAddrRange());
}
+ /**
+ * Range used by memory-mapped m5 pseudo-ops if enabled. Returns
+ * an invalid/empty range if disabled.
+ */
+ const AddrRange &m5opRange() const { return _m5opRange; }
+
/** Returns true if the system of a specific thread context implements
the
* Security Extensions
*/
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index eeccca0..6f7998d 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -55,6 +55,7 @@
#include "arch/arm/system.hh"
#include "arch/arm/table_walker.hh"
#include "arch/arm/utility.hh"
+#include "arch/generic/mmapped_ipr.hh"
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
@@ -81,12 +82,17 @@
isHyp(false), asid(0), vmid(0), dacr(0),
miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
{
+ const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys);
+
tableWalker->setTlb(this);
// Cache system-level properties
haveLPAE = tableWalker->haveLPAE();
haveVirtualization = tableWalker->haveVirtualization();
haveLargeAsid64 = tableWalker->haveLargeAsid64();
+
+ if (sys)
+ m5opRange = sys->m5opRange();
}
TLB::~TLB()
@@ -129,6 +135,15 @@
Fault
TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
{
+ const Addr paddr = req->getPaddr();
+
+ if (m5opRange.contains(paddr)) {
+ req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
+ req->setPaddr(GenericISA::iprAddressPseudoInst(
+ (paddr >> 8) & 0xFF,
+ paddr & 0xFF));
+ }
+
return NoFault;
}
@@ -582,7 +597,7 @@
return std::make_shared<GenericPageTableFault>(vaddr_tainted);
req->setPaddr(paddr);
- return NoFault;
+ return finalizePhysical(req, tc, mode);
}
Fault
@@ -1108,14 +1123,18 @@
fault = testTranslation(req, mode, te->domain);
}
- // Generate Illegal Inst Set State fault if IL bit is set in CPSR
if (fault == NoFault) {
+ // Generate Illegal Inst Set State fault if IL bit is set in CPSR
if (aarch64 && is_fetch && cpsr.il == 1) {
return std::make_shared<IllegalInstSetStateFault>();
}
- }
- return fault;
+ // Don't try to finalize a physical address unless the
+ // translation has completed (i.e., there is a table entry).
+ return te ? finalizePhysical(req, tc, mode) : NoFault;
+ } else {
+ return fault;
+ }
}
Fault
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index f4530a2..f5849f3 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -393,6 +393,8 @@
bool haveVirtualization;
bool haveLargeAsid64;
+ AddrRange m5opRange;
+
void updateMiscReg(ThreadContext *tc,
ArmTranslationType tranType = NormalTran);
--
To view, visit https://gem5-review.googlesource.com/2964
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2
Gerrit-Change-Number: 2964
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
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