Hi, I understand that there is no support for cortex-M architecture right now and neither Gem-5 is cycle accurate? right? or I have another question regarding the memory!
I have seen this paper <http://worldcomp-proceedings.com/proc/p2016/BIE4018.pdf> for example. which subsumes that cortex M architecture is the subset of cortex A architecture in terms of the instruction set (Thumb) and they do their simulations with gem5 for cortex-M4 I am also curious about memory figures: Can gem-5 provide the RAM taken by the code running on some architecture (Cortex-A lets say which is supported)? Best, Fahad On Thu, Oct 26, 2017 at 4:12 PM, Andreas Sandberg <[email protected]> wrote: > Hi Fahad, > > There is currently no support for the Arm M profile in gem5. Supporting > the M profile (Cortex M4 or other microcontrollers) would require quite > a bit of work since they have a system architecture that differs from A > class. The biggest difference is in interrupt handling. M-class does > automatic stack management and makes interrupts look like function calls > in C. Another large difference is is the way memory management works > where M class uses a range-based memory protection unit instead of a > full-blown MMU. > > gem5 should support most instructions supported by the M4 since M-class > mostly just uses a subset of Thumb. There might be some M-class specific > instructions missing though. > > If you want cycle accurate results, you might be better off just > requesting the RTL though the ARM University Program [1]. That'd allow > you to run a truly cycle accurate RTL simulation instead. Both M0 and M3 > RTL are currently available and can be downloaded for free for teaching > and research. If you really need access to an accurate M4 > representation, you could ask your professor to get in touch with the > University Program. > > Cheers, > Andreas > > [1] https://developer.arm.com/products/designstart/university-program > > > > On 26/10/2017 14:57, Fahad Butt wrote: > >> Hi all, >> >> I am searching for cycle accurate free simulators for my thesis work and >> have few questions regarding GEM5: >> >> 1- is It supporting Cortex-M4 architecture processor by ARM? >> 2- does it have FP and DSP instructions support? >> 3- can it be cycle accurate if i will simulate my code for cortex M4 >> processor(if it is supported) >> 4- can it give me memory figures? Like RAM while the code is executing? >> >> Hope to get a quick and detailed reply. It will help me moving forward >> quickly. >> >> Thank you. >> >> >> Best regards, >> Fahad masood >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
