Also, the "bootloader" is a very simple stub of code, so you shouldn't feel intimidated about modifying it. It's not a big fancy BIOS or UBoot or anything like that.
Gabe On Tue, Nov 7, 2017 at 5:39 AM, Andreas Sandberg <[email protected]> wrote: > Hi Fahad, > > I would argue that gem5 can never be cycle accurate, it can only be > cycle approximate. To be fully cycle accurate, you pretty much need to > simulate the RTL or something the is extremely close to RTL. Having said > that, making an extremely accurate cycle approximate model of an M-class > core should be reasonably easy compared to an A class core since the > pipeline is a lot simpler (in-order, typically single issue, handful of > stages) and the memory is typically fixed latency. You could probably > get a reasonably good approximation using the SimpleTiming or > SimpleAtomic CPU. > > In most cases, M profile instructions are a subset of the thumb-mode in > the A profile. However, the system architecture is very different. The > biggest limitation is that gem5 can't deliver interrupts according to > the M profile and it doesn't support the (optional) memory protection > unit in the M profile. If you don't need any of those, you might be > fine. You'll probably just need to make sure that gem5 boots in aarch32 > and switches to thumb state (the easiest way to do this would be to hack > the boot loader). After that, you simply load your elf into memory and > the boot loader should branch to the entry point. > > I'm not sure what you mean by "RAM taken by the code". What I think > you're after is the memory footprint of the application. We don't > normally report that, but there is a MemFootprintProbe that you can > attach to the memory system to count the number of unique pages that the > code touches. This will overestimate the memory usage though since you > don't really have the notion of a page on a microcontroller. > > Cheers, > Andreas > > > On 05/11/2017 14:29, fahad butt wrote: > >> Hi, >> >> I understand that there is no support for cortex-M architecture right now >> and neither Gem-5 is cycle accurate? right? or I have another question >> regarding the memory! >> >> I have seen this paper >> <http://worldcomp-proceedings.com/proc/p2016/BIE4018.pdf> for example. >> which subsumes that cortex M architecture is the subset of cortex A >> architecture in terms of the instruction set (Thumb) and they do their >> simulations with gem5 for cortex-M4 >> >> I am also curious about memory figures: >> Can gem-5 provide the RAM taken by the code running on some architecture >> (Cortex-A lets say which is supported)? >> >> Best, >> Fahad >> >> On Thu, Oct 26, 2017 at 4:12 PM, Andreas Sandberg < >> [email protected]> >> wrote: >> >> Hi Fahad, >>> >>> There is currently no support for the Arm M profile in gem5. Supporting >>> the M profile (Cortex M4 or other microcontrollers) would require quite >>> a bit of work since they have a system architecture that differs from A >>> class. The biggest difference is in interrupt handling. M-class does >>> automatic stack management and makes interrupts look like function calls >>> in C. Another large difference is is the way memory management works >>> where M class uses a range-based memory protection unit instead of a >>> full-blown MMU. >>> >>> gem5 should support most instructions supported by the M4 since M-class >>> mostly just uses a subset of Thumb. There might be some M-class specific >>> instructions missing though. >>> >>> If you want cycle accurate results, you might be better off just >>> requesting the RTL though the ARM University Program [1]. That'd allow >>> you to run a truly cycle accurate RTL simulation instead. Both M0 and M3 >>> RTL are currently available and can be downloaded for free for teaching >>> and research. If you really need access to an accurate M4 >>> representation, you could ask your professor to get in touch with the >>> University Program. >>> >>> Cheers, >>> Andreas >>> >>> [1] https://developer.arm.com/products/designstart/university-program >>> >>> >>> >>> On 26/10/2017 14:57, Fahad Butt wrote: >>> >>> Hi all, >>>> >>>> I am searching for cycle accurate free simulators for my thesis work and >>>> have few questions regarding GEM5: >>>> >>>> 1- is It supporting Cortex-M4 architecture processor by ARM? >>>> 2- does it have FP and DSP instructions support? >>>> 3- can it be cycle accurate if i will simulate my code for cortex M4 >>>> processor(if it is supported) >>>> 4- can it give me memory figures? Like RAM while the code is executing? >>>> >>>> Hope to get a quick and detailed reply. It will help me moving forward >>>> quickly. >>>> >>>> Thank you. >>>> >>>> >>>> Best regards, >>>> Fahad masood >>>> _______________________________________________ >>>> gem5-dev mailing list >>>> [email protected] >>>> http://m5sim.org/mailman/listinfo/gem5-dev >>>> >>>> IMPORTANT NOTICE: The contents of this email and any attachments are >>> confidential and may also be privileged. If you are not the intended >>> recipient, please notify the sender immediately and do not disclose the >>> contents to any other person, use it for any purpose, or store or copy >>> the >>> information in any medium. Thank you. >>> _______________________________________________ >>> gem5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/gem5-dev >>> >> _______________________________________________ >> gem5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/gem5-dev >> > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
