Andreas Sandberg has uploaded this change for review. (
https://gem5-review.googlesource.com/5742
Change subject: arch-arm, sim: Introduce power management m5op
......................................................................
arch-arm, sim: Introduce power management m5op
Create a new pseudo instruction solely reserved for power management
activities. In the Arm arch the pseudo instruction takes two
parameters m5_power(int op, int cpuid). The first parameter being the
power function requested and the second a cpuid for when
the information is required. A header to share macros between
simulated workload and simulator was added at include/asm/generic .
Change-Id: Ic6bfecbd69d06b66385135b35b143aa829fa67ff
Reviewed-by: Andreas Sandberg <[email protected]>
---
M include/gem5/asm/generic/m5ops.h
A include/gem5/asm/generic/power.h
M include/gem5/m5ops.h
M src/arch/arm/isa/formats/aarch64.isa
M src/arch/arm/isa/formats/m5ops.isa
M src/arch/arm/isa/insts/m5ops.isa
M src/sim/pseudo_inst.cc
M src/sim/pseudo_inst.hh
8 files changed, 156 insertions(+), 5 deletions(-)
diff --git a/include/gem5/asm/generic/m5ops.h
b/include/gem5/asm/generic/m5ops.h
index 81569e0..8161e09 100644
--- a/include/gem5/asm/generic/m5ops.h
+++ b/include/gem5/asm/generic/m5ops.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 ARM Limited
+ * Copyright (c) 2016-2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -84,6 +84,7 @@
#define M5OP_SE_PAGE_FAULT 0x61
#define M5OP_DIST_TOGGLE_SYNC 0x62
+#define M5OP_POWER 0x63
// These operations are for critical path annotation
#define M5OP_ANNOTATE 0x55
#define M5OP_AN_BSM 0x1
@@ -110,6 +111,7 @@
M5OP(m5_quiesce_ns, M5OP_QUIESCE_NS, 0); \
M5OP(m5_quiesce_cycle, M5OP_QUIESCE_CYCLE, 0); \
M5OP(m5_quiesce_time, M5OP_QUIESCE_TIME, 0); \
+ M5OP(m5_power, M5OP_POWER, 0); \
M5OP(m5_rpns, M5OP_RPNS, 0); \
M5OP(m5_wake_cpu, M5OP_WAKE_CPU, 0); \
M5OP(m5_exit, M5OP_EXIT, 0); \
diff --git a/include/gem5/asm/generic/power.h
b/include/gem5/asm/generic/power.h
new file mode 100644
index 0000000..341e5a2
--- /dev/null
+++ b/include/gem5/asm/generic/power.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Jose Marinho
+ *
+ */
+
+#ifndef __INCLUDE_ASM_GENERIC_POWER_HH__
+#define __INCLUDE_ASM_GENERIC_POWER_HH__
+
+#define GEM5_POWER_RETURN_SUCCESS 0
+#define GEM5_POWER_RETURN_ERROR -1
+#define GEM5_POWER_RETURN_WRONG_ARGS -2
+#define GEM5_POWER_RETURN_NOTHING_DONE -3
+
+#define GEM5_POWER_CPU_SUSPEND 1
+#define GEM5_POWER_CPU_OFF 2
+#define GEM5_POWER_CPU_ON 3
+
+#endif // __INCLUDE_ASM_GENERIC_POWER_HH__
+
diff --git a/include/gem5/m5ops.h b/include/gem5/m5ops.h
index 5062ac2..f28829a 100644
--- a/include/gem5/m5ops.h
+++ b/include/gem5/m5ops.h
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2017 ARM Limited
* Copyright (c) 2003-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -64,6 +65,7 @@
void m5_add_symbol(uint64_t addr, char *symbol);
void m5_loadsymbol();
void m5_panic(void);
+int32_t m5_power(uint64_t function, uint64_t cpuid);
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
diff --git a/src/arch/arm/isa/formats/aarch64.isa
b/src/arch/arm/isa/formats/aarch64.isa
index 2c33e24..177acf6 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -2042,6 +2042,8 @@
case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
case M5OP_ADD_SYMBOL: return new M5addsymbol64(machInst);
case M5OP_PANIC: return new M5panic(machInst);
+ case M5OP_POWER: return new PowerManagementCPU64(machInst);
+
case M5OP_WORK_BEGIN: return new M5workbegin64(machInst);
case M5OP_WORK_END: return new M5workend64(machInst);
default: return new Unknown64(machInst);
diff --git a/src/arch/arm/isa/formats/m5ops.isa
b/src/arch/arm/isa/formats/m5ops.isa
index d3db813..369c6a0 100644
--- a/src/arch/arm/isa/formats/m5ops.isa
+++ b/src/arch/arm/isa/formats/m5ops.isa
@@ -1,5 +1,5 @@
//
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010, 2017 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -66,6 +66,8 @@
case M5OP_SWITCH_CPU: return new M5switchcpu(machInst);
case M5OP_ADD_SYMBOL: return new M5addsymbol(machInst);
case M5OP_PANIC: return new M5panic(machInst);
+ case M5OP_POWER: return new PowerManagementCPU(machInst);
+
case M5OP_WORK_BEGIN: return new M5workbegin(machInst);
case M5OP_WORK_END: return new M5workend(machInst);
}
diff --git a/src/arch/arm/isa/insts/m5ops.isa
b/src/arch/arm/isa/insts/m5ops.isa
index e931478..34d2df8 100644
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -1,5 +1,5 @@
//
-// Copyright (c) 2010, 2012-2013 ARM Limited
+// Copyright (c) 2010, 2012-2013, 2017 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -578,4 +578,32 @@
header_output += BasicDeclare.subst(m5workendIop)
decoder_output += BasicConstructor.subst(m5workendIop)
exec_output += PredOpExecute.subst(m5workendIop)
+
+ powerManagement = '''
+ R0 = PseudoInst::powerManagementCPU(xc->tcBase(), join32to64(R0, R1),
+ join32to64(R2,R3));
+ '''
+
+ powerManagement64 = '''
+ X0 = PseudoInst::powerManagementCPU(xc->tcBase(), X0, X1);
+ '''
+
+ powerManagementCPUIop = InstObjParams("powerManagementCPU",
+ "PowerManagementCPU", "PredOp",
+ { "code": powerManagement,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(powerManagementCPUIop)
+ decoder_output += BasicConstructor.subst(powerManagementCPUIop)
+ exec_output += PredOpExecute.subst(powerManagementCPUIop)
+
+ powerManagementCPUIop = InstObjParams("powerManagementCPU",
+ "PowerManagementCPU64", "PredOp",
+ { "code": powerManagement64,
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative", "IsUnverifiable"])
+ header_output += BasicDeclare.subst(powerManagementCPUIop)
+ decoder_output += BasicConstructor.subst(powerManagementCPUIop)
+ exec_output += PredOpExecute.subst(powerManagementCPUIop)
+
}};
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index dc37a8c..5d7589a 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -52,6 +52,7 @@
#include <vector>
#include <gem5/asm/generic/m5ops.h>
+#include <gem5/asm/generic/power.h>
#include "arch/kernel_stats.hh"
#include "arch/pseudo_inst.hh"
@@ -189,6 +190,9 @@
case M5OP_PANIC:
panic("M5 panic instruction called at %s\n", tc->pcState());
+ case M5OP_POWER:
+ return powerManagementCPU(tc, args[0], args[1]);
+
case M5OP_WORK_BEGIN:
workbegin(tc, args[0], args[1]);
break;
@@ -716,4 +720,60 @@
}
}
+
+// Function used to control the power state of cores from software.
+// The cpuid input parameter must be an index to the thread context array.
+//
+int32_t
+powerManagementCPU(ThreadContext *requester_tc, uint64_t function,
+ uint64_t cpuid)
+{
+ DPRINTF(PseudoInst, "PseudoInst::powerManagementCPU(%i)\n", function);
+
+ System *sys = requester_tc->getSystemPtr();
+
+ if (sys->numContexts() <= cpuid) {
+ warn("PseudoInst::powerManagementCPU(%i), cpuid greater than"
+ " number of contexts(%i)\n",cpuid, sys->numContexts());
+ return GEM5_POWER_RETURN_WRONG_ARGS;
+ }
+
+ ThreadContext *tc = sys->threadContexts[cpuid];
+
+ switch (function) {
+
+ case GEM5_POWER_CPU_SUSPEND:
+ DPRINTF(PseudoInst, "PseudoInst::powerManagementCPU() cpu %d"
+ " suspend\n", cpuid);
+
+ tc->quiesce();
+ tc->getCpuPtr()->schedulePowerGatingEvent();
+
+ return GEM5_POWER_RETURN_SUCCESS;
+
+ case GEM5_POWER_CPU_OFF:
+ DPRINTF(PseudoInst, "PseudoInst::powerManagementCPU() cpu %d"
+ " OFF\n", cpuid);
+
+ tc->quiesce();
+ tc->getCpuPtr()->schedulePowerGatingEvent();
+
+ return GEM5_POWER_RETURN_SUCCESS;
+
+ case GEM5_POWER_CPU_ON:
+ DPRINTF(PseudoInst, "PseudoInst::powerManagementCPU() cpu %d"
+ " ON\n", cpuid);
+
+ if (tc->status() == ThreadContext::Active) {
+ return GEM5_POWER_RETURN_WRONG_ARGS;
+ }
+
+ tc->activate();
+ return GEM5_POWER_RETURN_SUCCESS;
+
+ default:
+ return GEM5_POWER_RETURN_WRONG_ARGS;
+ }
+}
+
} // namespace PseudoInst
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index d9b981f..4e471d0 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012, 2017 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -89,7 +89,8 @@
void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid);
void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid);
void togglesync(ThreadContext *tc);
-
+int32_t powerManagementCPU(ThreadContext *tc, uint64_t function,
+ uint64_t cpuid);
} // namespace PseudoInst
#endif // __SIM_PSEUDO_INST_HH__
--
To view, visit https://gem5-review.googlesource.com/5742
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic6bfecbd69d06b66385135b35b143aa829fa67ff
Gerrit-Change-Number: 5742
Gerrit-PatchSet: 1
Gerrit-Owner: Andreas Sandberg <[email protected]>
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
