Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6022
Change subject: arch-riscv: Move standard ops out of ISA
......................................................................
arch-riscv: Move standard ops out of ISA
This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamicallly-generated content is left behind for each individual
instruction's implementation.
Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
---
M src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/bitfields.hh
A src/arch/riscv/insts/standard.cc
A src/arch/riscv/insts/standard.hh
M src/arch/riscv/isa/formats/standard.isa
M src/arch/riscv/isa/includes.isa
6 files changed, 178 insertions(+), 141 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
index 95e6afd..fe90280 100644
--- a/src/arch/riscv/insts/SConscript
+++ b/src/arch/riscv/insts/SConscript
@@ -1,4 +1,5 @@
Import('*')
if env['TARGET_ISA'] == 'riscv':
+ Source('standard.cc')
Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/bitfields.hh
b/src/arch/riscv/insts/bitfields.hh
new file mode 100644
index 0000000..45744e0
--- /dev/null
+++ b/src/arch/riscv/insts/bitfields.hh
@@ -0,0 +1,9 @@
+#ifndef __ARCH_RISCV_BITFIELDS_HH__
+#define __ARCH_RISCV_BITFIELDS_HH__
+
+#include "base/bitfield.hh"
+
+#define CSRIMM bits(machInst, 19, 15)
+#define FUNCT12 bits(machInst, 31, 20)
+
+#endif // __ARCH_RISCV_BITFIELDS_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
new file mode 100644
index 0000000..a87fb7a
--- /dev/null
+++ b/src/arch/riscv/insts/standard.cc
@@ -0,0 +1,36 @@
+#include "arch/riscv/insts/standard.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+ registerName(_srcRegIdx[0]) << ", " <<
+ registerName(_srcRegIdx[1]);
+ return ss.str();
+}
+
+string
+CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ stringstream ss;
+ ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+ if (_numSrcRegs > 0)
+ ss << registerName(_srcRegIdx[0]) << ", ";
+ ss << MiscRegNames.at(csr);
+ return ss.str();
+}
+
+}
\ No newline at end of file
diff --git a/src/arch/riscv/insts/standard.hh
b/src/arch/riscv/insts/standard.hh
new file mode 100644
index 0000000..e8fc63f
--- /dev/null
+++ b/src/arch/riscv/insts/standard.hh
@@ -0,0 +1,131 @@
+#ifndef __ARCH_RISCV_STANDARD_INST_HH__
+#define __ARCH_RISCV_STANDARD_INST_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for operations that work only on registers
+ */
+class RegOp : public RiscvStaticInst
+{
+ protected:
+ /// Constructor
+ RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass)
+ {}
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+/**
+ * Base class for operations with signed immediates
+ */
+class ImmOp : public RiscvStaticInst
+{
+ protected:
+ int64_t imm;
+
+ /// Constructor
+ ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+ {}
+
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for operations with unsigned immediates
+ */
+class UImmOp : public RiscvStaticInst
+{
+ protected:
+ uint64_t imm;
+
+ /// Constructor
+ UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+ {}
+
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for operations with branching
+ */
+class BranchOp : public ImmOp
+{
+ protected:
+ /// Constructor
+ BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : ImmOp(mnem, _machInst, __opClass)
+ {}
+
+ using StaticInst::branchTarget;
+
+ virtual RiscvISA::PCState
+ branchTarget(ThreadContext *tc) const
+ {
+ return StaticInst::branchTarget(tc);
+ }
+
+ virtual RiscvISA::PCState
+ branchTarget(const RiscvISA::PCState &branchPC) const
+ {
+ return StaticInst::branchTarget(branchPC);
+ }
+
+ virtual std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
+};
+
+/**
+ * Base class for system operations
+ */
+class SystemOp : public RiscvStaticInst
+{
+ protected:
+ /// Constructor
+ SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass)
+ {}
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ return mnemonic;
+ }
+};
+
+/**
+ * Base class for CSR operations
+ */
+class CSROp : public RiscvStaticInst
+{
+ protected:
+ uint64_t csr;
+ uint64_t uimm;
+
+ /// Constructor
+ CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : RiscvStaticInst(mnem, _machInst, __opClass),
+ csr(FUNCT12), uimm(CSRIMM)
+ {}
+
+ std::string
+ generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
+}
+
+#endif // __ARCH_RISCV_STANDARD_INST_HH__
\ No newline at end of file
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 35c3fa8..3bcbe6d 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -33,147 +33,6 @@
//
// Integer instructions
//
-output header {{
- /**
- * Base class for operations that work only on registers
- */
- class RegOp : public RiscvStaticInst
- {
- protected:
- /// Constructor
- RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-
- /**
- * Base class for operations with signed immediates
- */
- class ImmOp : public RiscvStaticInst
- {
- protected:
- int64_t imm;
-
- /// Constructor
- ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
- {}
-
- virtual std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
- };
-
- /**
- * Base class for operations with unsigned immediates
- */
- class UImmOp : public RiscvStaticInst
- {
- protected:
- uint64_t imm;
-
- /// Constructor
- UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
- {}
-
- virtual std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
- };
-
- /**
- * Base class for operations with branching
- */
- class BranchOp : public ImmOp
- {
- protected:
- /// Constructor
- BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : ImmOp(mnem, _machInst, __opClass)
- {}
-
- using StaticInst::branchTarget;
-
- virtual RiscvISA::PCState
- branchTarget(ThreadContext *tc) const
- {
- return StaticInst::branchTarget(tc);
- }
-
- virtual RiscvISA::PCState
- branchTarget(const RiscvISA::PCState &branchPC) const
- {
- return StaticInst::branchTarget(branchPC);
- }
-
- virtual std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
- };
-
- /**
- * Base class for system operations
- */
- class SystemOp : public RiscvStaticInst
- {
- public:
- /// Constructor
- SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return mnemonic;
- }
- };
-
- /**
- * Base class for CSR operations
- */
- class CSROp : public RiscvStaticInst
- {
- protected:
- uint64_t csr;
- uint64_t uimm;
-
- public:
- /// Constructor
- CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
- : RiscvStaticInst(mnem, _machInst, __opClass),
- csr(FUNCT12), uimm(CSRIMM)
- {}
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
-//Outputs to decoder.cc
-output decoder {{
- std::string
- RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[1]);
- return ss.str();
- }
-
- std::string
- CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- std::stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
- if (_numSrcRegs > 0)
- ss << registerName(_srcRegIdx[0]) << ", ";
- ss << MiscRegNames.at(csr);
- return ss.str();
- }
-}};
def template ImmDeclare {{
//
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index 48f2b19..dfd0f37 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,6 +42,7 @@
#include <tuple>
#include <vector>
+#include "arch/riscv/insts/standard.hh"
#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Gerrit-Change-Number: 6022
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
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