Alec Roelke has uploaded this change for review. (
https://gem5-review.googlesource.com/6021
Change subject: arch-riscv: Move static_inst into a directory
......................................................................
arch-riscv: Move static_inst into a directory
This patch creates an "insts" directory in src/arch/riscv to store
static portions of instruction definitions that aren't part of the code
generated by the ISA description. It serves as a starting point for
future patches to simplify the ISA description.
Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
---
A src/arch/riscv/insts/SConscript
A src/arch/riscv/insts/static_inst.cc
R src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/includes.isa
4 files changed, 37 insertions(+), 33 deletions(-)
diff --git a/src/arch/riscv/insts/SConscript
b/src/arch/riscv/insts/SConscript
new file mode 100644
index 0000000..95e6afd
--- /dev/null
+++ b/src/arch/riscv/insts/SConscript
@@ -0,0 +1,4 @@
+Import('*')
+
+if env['TARGET_ISA'] == 'riscv':
+ Source('static_inst.cc')
\ No newline at end of file
diff --git a/src/arch/riscv/insts/static_inst.cc
b/src/arch/riscv/insts/static_inst.cc
new file mode 100644
index 0000000..8fc396d
--- /dev/null
+++ b/src/arch/riscv/insts/static_inst.cc
@@ -0,0 +1,19 @@
+#include "arch/riscv/insts/static_inst.hh"
+
+#include "arch/riscv/types.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+void
+RiscvMicroInst::advancePC(PCState &pcState) const
+{
+ if (flags[IsLastMicroop]) {
+ pcState.uEnd();
+ } else {
+ pcState.uAdvance();
+ }
+}
+
+} // namespace RiscvISA
\ No newline at end of file
diff --git a/src/arch/riscv/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
similarity index 80%
rename from src/arch/riscv/static_inst.hh
rename to src/arch/riscv/insts/static_inst.hh
index bdcdee7..d360d44 100644
--- a/src/arch/riscv/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -33,12 +33,15 @@
#ifndef __ARCH_RISCV_STATIC_INST_HH__
#define __ARCH_RISCV_STATIC_INST_HH__
-////////////////////////////////////////////////////////////////////
-//
-// Base class for Riscv instructions, and some support functions
-//
+#include <string>
-namespace RiscvISA {
+#include "arch/riscv/types.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+
+namespace RiscvISA
+{
/**
* Base class for all RISC-V static instructions.
@@ -46,20 +49,13 @@
class RiscvStaticInst : public StaticInst
{
protected:
- // Constructor
- RiscvStaticInst(const char *mnem, MachInst _machInst,
- OpClass __opClass) : StaticInst(mnem, _machInst, __opClass)
- {}
+ using StaticInst::StaticInst;
virtual std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
public:
- void
- advancePC(RiscvISA::PCState &pc) const
- {
- pc.advance();
- }
+ void advancePC(PCState &pc) const { pc.advance(); }
};
/**
@@ -78,16 +74,9 @@
flags[IsMacroop] = true;
}
- ~RiscvMacroInst()
- {
- microops.clear();
- }
+ ~RiscvMacroInst() { microops.clear(); }
- StaticInstPtr
- fetchMicroop(MicroPC upc) const
- {
- return microops[upc];
- }
+ StaticInstPtr fetchMicroop(MicroPC upc) const { return microops[upc]; }
Fault
initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
@@ -123,15 +112,7 @@
flags[IsMicroop] = true;
}
- void
- advancePC(RiscvISA::PCState &pcState) const
- {
- if (flags[IsLastMicroop]) {
- pcState.uEnd();
- } else {
- pcState.uAdvance();
- }
- }
+ void advancePC(PCState &pcState) const;
};
}
diff --git a/src/arch/riscv/isa/includes.isa
b/src/arch/riscv/isa/includes.isa
index c172d03..48f2b19 100644
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -42,7 +42,7 @@
#include <tuple>
#include <vector>
-#include "arch/riscv/static_inst.hh"
+#include "arch/riscv/insts/static_inst.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa
Gerrit-Change-Number: 6021
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <ar...@virginia.edu>
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