Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/6821
Change subject: alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of
ISA_HAS_DELAY_SLOT.
......................................................................
alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.
This constant is, first, a #define, and second only used in one place.
The O3 CPU is complex enough that a small hint that an if can be
skipped likely won't have any impact on performance. By getting rid of
this constant, we remove one small way non-ISA components are ISA
specific.
Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
---
M src/arch/alpha/isa_traits.hh
M src/arch/arm/isa_traits.hh
M src/arch/mips/isa_traits.hh
M src/arch/power/isa_traits.hh
M src/arch/riscv/isa_traits.hh
M src/arch/sparc/isa_traits.hh
M src/arch/x86/isa_traits.hh
M src/cpu/o3/fetch_impl.hh
8 files changed, 1 insertion(+), 22 deletions(-)
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index f1c39cb..a383fe4 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -45,9 +45,6 @@
StaticInstPtr decodeInst(ExtMachInst);
-// Alpha Does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr PageMask = ~(PageBytes - 1);
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 8be2bf0..185c764 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -57,9 +57,6 @@
StaticInstPtr decodeInst(ExtMachInst);
- // ARM DOES NOT have a delay slot
- #define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index ca375f2..c0b1b9d 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -47,9 +47,6 @@
StaticInstPtr decodeInst(ExtMachInst);
-// MIPS DOES have a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 3abc831..fa13483 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -48,9 +48,6 @@
StaticInstPtr decodeInst(ExtMachInst);
-// POWER DOES NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const Addr Page_Mask = ~(PageBytes - 1);
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 327d644..93f984b 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -57,9 +57,6 @@
using namespace LittleEndianGuest;
-// Riscv does NOT have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index b925386..0db5a12 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
-// SPARC has a delay slot
-#define ISA_HAS_DELAY_SLOT 1
-
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 88cd16e..00c5e9b 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -53,9 +53,6 @@
//are used.
using namespace LittleEndianGuest;
- // X86 does not have a delay slot
-#define ISA_HAS_DELAY_SLOT 0
-
// X86 NOP (XCHG rAX, rAX)
//XXX This needs to be set to an intermediate instruction struct
//which encodes this instruction
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 7631b4c..17dd992 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1277,7 +1277,7 @@
break;
}
- if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
+ if (pcOffset == 0) {
// Walk past any annulled delay slot instructions.
Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
while (fetchAddr != pcAddr && blkOffset < numInsts) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I820ebc9df10aeb4fcb69c12f6a784e9ec616743c
Gerrit-Change-Number: 6821
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
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