Giacomo Travaglini merged this change by Chuan Zhu. ( https://gem5-review.googlesource.com/8081 )

Change subject: arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64
......................................................................

arch-arm: Fix Secure state check in checkFPAdvSIMDTrap64

The old code does secure state check by using "el <= EL2", which
mis-considers secure EL1 and EL0. This patch fixes this by using
inSecureState as in ARM ARM.

Change-Id: I01d847c6af022c1462b16206cbc576f15f5569fd
Reviewed-by: Jack Travaglini <giacomo.travagl...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8081
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/insts/static_inst.cc
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index a7ba91e..40a1fe4 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -629,9 +629,7 @@
 Fault
 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
 {
-    const ExceptionLevel el = (ExceptionLevel) (uint8_t)cpsr.el;
-
-    if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
+    if (ArmSystem::haveVirtualization(tc) && !inSecureState(tc)) {
         HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
         if (cptrEnCheck.tfp)
             return advSIMDFPAccessTrap64(EL2);

--
To view, visit https://gem5-review.googlesource.com/8081
To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings

Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I01d847c6af022c1462b16206cbc576f15f5569fd
Gerrit-Change-Number: 8081
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev

Reply via email to