Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

    https://gem5-review.googlesource.com/8371

to review the following change.


Change subject: arch-arm: Add AArch32 SVC Semihosting interface
......................................................................

arch-arm: Add AArch32 SVC Semihosting interface

AArch32 Svc instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
---
M src/arch/arm/isa/insts/misc.isa
1 file changed, 15 insertions(+), 4 deletions(-)



diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index cf3d0e0..566ea4b 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,15 +40,26 @@
 let {{

     svcCode = '''
-    fault = std::make_shared<SupervisorCall>(machInst, imm);
+    ThreadContext *tc = xc->tcBase();
+
+    const auto semihost_imm = Thumb? 0xAB : 0x123456;
+
+    if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
+        R0 = ArmSystem::callSemihosting32(tc, R0, R1);
+    } else {
+        fault = std::make_shared<SupervisorCall>(machInst, imm);
+    }
     '''

     svcIop = InstObjParams("svc", "Svc", "ImmOp",
                            { "code": svcCode,
-                             "predicate_test": predicateTest },
- ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
+                             "predicate_test": predicateTest,
+                             "thumb_semihost": '0xAB',
+                             "arm_semihost": '0x123456' },
+                           ["IsSyscall", "IsNonSpeculative",
+                            "IsSerializeAfter"])
     header_output = ImmOpDeclare.subst(svcIop)
-    decoder_output = ImmOpConstructor.subst(svcIop)
+    decoder_output = SemihostConstructor.subst(svcIop)
     exec_output = PredOpExecute.subst(svcIop)

     smcCode = '''

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3
Gerrit-Change-Number: 8371
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
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