Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/9404 )
Change subject: cpu: Remove ExtMachInst typedefs from the O3 CPU model.
......................................................................
cpu: Remove ExtMachInst typedefs from the O3 CPU model.
These typedefs aren't used, and they expose ISA specific types outside
the ISA implementations.
Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Reviewed-on: https://gem5-review.googlesource.com/9404
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Gabe Black <[email protected]>
---
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/fetch.hh
2 files changed, 0 insertions(+), 3 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved
Gabe Black: Looks good to me, approved
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8a0ae1d..47dc830 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -65,8 +65,6 @@
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
- /** Extended machine instruction type. */
- typedef TheISA::ExtMachInst ExtMachInst;
/** Register types. */
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 672fb49..4382197 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -83,7 +83,6 @@
/** Typedefs from ISA. */
typedef TheISA::MachInst MachInst;
- typedef TheISA::ExtMachInst ExtMachInst;
class FetchTranslation : public BaseTLB::Translation
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I64b9cec18d6f92765eebbdf8c8f1de15c0deba34
Gerrit-Change-Number: 9404
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: merged
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