Hello Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/10321
to look at the new patch set (#2).
Change subject: arch-x86: LFENCE should be a serializing instruction. Make
it so
......................................................................
arch-x86: LFENCE should be a serializing instruction. Make it so
According to the Intel SDM, no instruction following an LFENCE can begin
execution until after the LFENCE has executed. (This is
less strict than an actual serializing instruction, such as CPUID.)
Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure
that no future instruction is fetched until after the serializing
instruction is completed.
By contrast, LFENCE (and other memory-ordering instructions) allows
future instructions to have been fetched; it just prohibits them from
being executed.
Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7
Signed-off-by: Isaac Richter <[email protected]>
---
M src/arch/x86/isa/decoder/two_byte_opcodes.isa
1 file changed, 2 insertions(+), 1 deletion(-)
--
To view, visit https://gem5-review.googlesource.com/10321
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7
Gerrit-Change-Number: 10321
Gerrit-PatchSet: 2
Gerrit-Owner: Isaac Richter <[email protected]>
Gerrit-Reviewer: Isaac Richter <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newpatchset
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
