Hello Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13064
to look at the new patch set (#2).
Change subject: arch-arm: Init AArch64 ID registers in SE mode
......................................................................
arch-arm: Init AArch64 ID registers in SE mode
One of the auxv vector's flag is the HWCAP, whose bits match the content
of several arm ID registers. This patch factors out AArch64 ID
registers init into a separate method and creates the symmetric AArch32
ID register init as well, so that we get a meaningful auxiliary vector
in SE mode.
Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 43 insertions(+), 22 deletions(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e
Gerrit-Change-Number: 13064
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newpatchset
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