Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13064 )
Change subject: arch-arm: Init AArch64 ID registers in SE mode
......................................................................
arch-arm: Init AArch64 ID registers in SE mode
One of the auxv vector's flag is the HWCAP, whose bits match the content
of several arm ID registers. This patch factors out AArch64 ID
registers init into a separate method and creates the symmetric AArch32
ID register init as well, so that we get a meaningful auxiliary vector
in SE mode.
Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/13064
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
2 files changed, 43 insertions(+), 22 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 9a4fb28..6063607 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -84,12 +84,12 @@
haveLPAE = system->haveLPAE();
haveVirtualization = system->haveVirtualization();
haveLargeAsid64 = system->haveLargeAsid64();
- physAddrRange64 = system->physAddrRange64();
+ physAddrRange = system->physAddrRange();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
haveLargeAsid64 = false;
- physAddrRange64 = 32; // dummy value
+ physAddrRange = 32; // dummy value
}
initializeMiscRegMetadata();
@@ -114,22 +114,13 @@
SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
memset(miscRegs, 0, sizeof(miscRegs));
- // Initialize configurable default values
- miscRegs[MISCREG_MIDR] = p->midr;
- miscRegs[MISCREG_MIDR_EL1] = p->midr;
- miscRegs[MISCREG_VPIDR] = p->midr;
+ initID32(p);
- miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
- miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
- miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
- miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
- miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
- miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
-
- miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
- miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
- miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
- miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+ // We always initialize AArch64 ID registers even
+ // if we are in AArch32. This is done since if we
+ // are in SE mode we don't know if our ArmProcess is
+ // AArch32 or AArch64
+ initID64(p);
if (FullSystem && system->highestELIs64()) {
// Initialize AArch64 state
@@ -290,7 +281,32 @@
// Always non-secure
miscRegs[MISCREG_SCR_EL3] = 1;
}
+}
+void
+ISA::initID32(const ArmISAParams *p)
+{
+ // Initialize configurable default values
+ miscRegs[MISCREG_MIDR] = p->midr;
+ miscRegs[MISCREG_MIDR_EL1] = p->midr;
+ miscRegs[MISCREG_VPIDR] = p->midr;
+
+ miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
+ miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
+ miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
+ miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
+ miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
+ miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
+
+ miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
+ miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
+ miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
+ miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
+}
+
+void
+ISA::initID64(const ArmISAParams *p)
+{
// Initialize configurable id registers
miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
@@ -326,7 +342,7 @@
// Physical address size
miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
- encodePhysAddrRange64(physAddrRange64));
+ encodePhysAddrRange64(physAddrRange));
}
void
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 7b39682..ae35d70 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -88,7 +88,7 @@
bool haveLPAE;
bool haveVirtualization;
bool haveLargeAsid64;
- uint8_t physAddrRange64;
+ uint8_t physAddrRange;
/**
* If true, accesses to IMPLEMENTATION DEFINED registers are
treated
@@ -409,8 +409,13 @@
public:
void clear();
- void clear64(const ArmISAParams *p);
+ protected:
+ void clear64(const ArmISAParams *p);
+ void initID32(const ArmISAParams *p);
+ void initID64(const ArmISAParams *p);
+
+ public:
MiscReg readMiscRegNoEffect(int misc_reg) const;
MiscReg readMiscReg(int misc_reg, ThreadContext *tc);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
@@ -642,7 +647,7 @@
SERIALIZE_SCALAR(haveLPAE);
SERIALIZE_SCALAR(haveVirtualization);
SERIALIZE_SCALAR(haveLargeAsid64);
- SERIALIZE_SCALAR(physAddrRange64);
+ SERIALIZE_SCALAR(physAddrRange);
}
void unserialize(CheckpointIn &cp)
{
@@ -656,7 +661,7 @@
UNSERIALIZE_SCALAR(haveLPAE);
UNSERIALIZE_SCALAR(haveVirtualization);
UNSERIALIZE_SCALAR(haveLargeAsid64);
- UNSERIALIZE_SCALAR(physAddrRange64);
+ UNSERIALIZE_SCALAR(physAddrRange);
}
void startup(ThreadContext *tc);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13064
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e
Gerrit-Change-Number: 13064
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
