Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13517
to review the following change.
Change subject: cpu-o3: Add cache read ports limit to LSQ
......................................................................
cpu-o3: Add cache read ports limit to LSQ
This change introduces cache read ports to limit the number of
per-cycle loads. Previously only the number of per-cycle stores
could be limited.
Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Signed-off-by: Gabor Dozsa <[email protected]>
Reviewed-by: Giacomo Gabrielli <[email protected]>
---
M src/cpu/o3/O3CPU.py
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit_impl.hh
4 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 434f7ce..3fb3dd3 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017 ARM Limited
+# Copyright (c) 2016-2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -67,7 +67,9 @@
activity = Param.Unsigned(0, "Initial count")
cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
- "Constrains stores only. Loads are constrained by load FUs.")
+ "Constrains stores only.")
+ cacheLoadPorts = Param.Unsigned(200, "Cache Ports. "
+ "Constrains loads only.")
decodeToFetchDelay = Param.Cycles(1, "Decode to fetch delay")
renameToFetchDelay = Param.Cycles(1 ,"Rename to fetch delay")
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 1feacda..a53f6a8 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -719,7 +719,7 @@
int entryAmount(ThreadID num_threads);
/** Ticks the LSQ. */
- void tick() { usedStorePorts = 0; }
+ void tick();
/** Inserts a load into the LSQ. */
void insertLoad(const DynInstPtr &load_inst);
@@ -928,9 +928,9 @@
/** Set D-cache blocked status */
void cacheBlocked(bool v);
/** Is any store port available to use? */
- bool storePortAvailable() const;
+ bool cachePortAvailable(bool is_load) const;
/** Another store port is in use */
- void storePortBusy();
+ void cachePortBusy(bool is_load);
protected:
/** D-cache is blocked */
@@ -939,6 +939,10 @@
int cacheStorePorts;
/** The number of used cache ports in this cycle by stores. */
int usedStorePorts;
+ /** The number of cache ports available each cycle (loads only). */
+ int cacheLoadPorts;
+ /** The number of used cache ports in this cycle by loads. */
+ int usedLoadPorts;
/** The LSQ policy for SMT mode. */
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 97d88df..eaa1b23 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -62,6 +62,7 @@
: cpu(cpu_ptr), iewStage(iew_ptr),
_cacheBlocked(false),
cacheStorePorts(params->cacheStorePorts), usedStorePorts(0),
+ cacheLoadPorts(params->cacheLoadPorts), usedLoadPorts(0),
lsqPolicy(readLSQPolicy(params->smtLSQPolicy)),
LQEntries(params->LQEntries),
SQEntries(params->SQEntries),
@@ -169,6 +170,18 @@
}
}
+template <class Impl>
+void
+LSQ<Impl>::tick()
+{
+ // Re-issue loads which got blocked on the per-cycle load ports limit.
+ if (usedLoadPorts == cacheLoadPorts && !_cacheBlocked)
+ iewStage->cacheUnblocked();
+
+ usedLoadPorts = 0;
+ usedStorePorts = 0;
+}
+
template<class Impl>
bool
LSQ<Impl>::cacheBlocked() const
@@ -185,17 +198,28 @@
template<class Impl>
bool
-LSQ<Impl>::storePortAvailable() const
+LSQ<Impl>::cachePortAvailable(bool is_load) const
{
- return usedStorePorts < cacheStorePorts;
+ bool ret;
+ if (is_load) {
+ ret = usedLoadPorts < cacheLoadPorts;
+ } else {
+ ret = usedStorePorts < cacheStorePorts;
+ }
+ return ret;
}
template<class Impl>
void
-LSQ<Impl>::storePortBusy()
+LSQ<Impl>::cachePortBusy(bool is_load)
{
- usedStorePorts++;
- assert(usedStorePorts <= cacheStorePorts);
+ if (is_load) {
+ usedLoadPorts++;
+ assert(usedLoadPorts <= cacheLoadPorts);
+ } else {
+ usedStorePorts++;
+ assert(usedStorePorts <= cacheStorePorts);
+ }
}
template<class Impl>
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index b906e4e..056297e 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -705,7 +705,7 @@
storeWBIt->valid() &&
storeWBIt->canWB() &&
((!needsTSO) || (!storeInFlight)) &&
- lsq->storePortAvailable()) {
+ lsq->cachePortAvailable(false)) {
if (isStoreBlocked) {
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
@@ -1037,20 +1037,22 @@
auto state = dynamic_cast<LSQSenderState*>(data_pkt->senderState);
- if (!lsq->cacheBlocked() && (isLoad || lsq->storePortAvailable())) {
- if (!dcachePort->sendTimingReq(data_pkt)) {
- ret = false;
- cache_got_blocked = true;
- }
- } else {
+ if (!lsq->cacheBlocked() &&
+ ((isLoad && lsq->cachePortAvailable(true)) ||
+ (!isLoad && lsq->cachePortAvailable(false)))) {
+ if (!dcachePort->sendTimingReq(data_pkt)) {
+ ret = false;
+ cache_got_blocked = true;
+ }
+ } else {
ret = false;
}
if (ret) {
if (!isLoad) {
- lsq->storePortBusy();
isStoreBlocked = false;
}
+ lsq->cachePortBusy(isLoad);
state->outstanding++;
state->request()->packetSent();
} else {
@@ -1064,7 +1066,6 @@
}
state->request()->packetNotSent();
}
-
return ret;
}
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/13517
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I39bbd984056c5a696725ee2db462a55b2079e2d4
Gerrit-Change-Number: 13517
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Gabor Dozsa <[email protected]>
Gerrit-MessageType: newchange
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