Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13697
Change subject: mem-cache: Add missing blk->whenReady of writes
......................................................................
mem-cache: Add missing blk->whenReady of writes
Blocks were being written to without updating the
whenReady variable.
Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <[email protected]>
---
M src/mem/cache/base.cc
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index ed23ffd..15f8ce7 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -755,6 +755,10 @@
if (overwrite_mem) {
std::memcpy(blk_data, &overwrite_val, pkt->getSize());
blk->status |= BlkDirty;
+
+ // Populate the time when the block will be ready to access
+ blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
+ pkt->payloadDelay;
}
}
@@ -871,6 +875,10 @@
// set block status to dirty
blk->status |= BlkDirty;
+
+ // Populate the time when the block will be ready to access
+ blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
+ pkt->payloadDelay;
} else {
cmpAndSwap(blk, pkt);
}
@@ -883,6 +891,10 @@
// Write or WriteLine at the first cache with block in writable
state
if (blk->checkWrite(pkt)) {
pkt->writeDataToBlock(blk->data, blkSize);
+
+ // Populate the time when the block will be ready to access
+ blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
+ pkt->payloadDelay;
}
// Always mark the line as dirty (and thus transition to the
// Modified state) even if we are a failed StoreCond so we
@@ -1035,7 +1047,7 @@
pkt->writeDataToBlock(blk->data, blkSize);
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
- // populate the time when the block will be ready to access.
+ // Populate the time when the block will be ready to access
blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
pkt->payloadDelay;
return true;
@@ -1092,7 +1104,7 @@
DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
incHitCount(pkt);
- // populate the time when the block will be ready to access.
+ // Populate the time when the block will be ready to access
blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
pkt->payloadDelay;
// if this a write-through packet it will be sent to cache
@@ -1225,10 +1237,11 @@
assert(pkt->getSize() == blkSize);
pkt->writeDataToBlock(blk->data, blkSize);
+
+ // Populate the time when the block will be ready to access
+ blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
+ pkt->payloadDelay;
}
- // We pay for fillLatency here.
- blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
- pkt->payloadDelay;
return blk;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Gerrit-Change-Number: 13697
Gerrit-PatchSet: 1
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-MessageType: newchange
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