Daniel Carvalho has uploaded a new patch set (#4) to the change originally
created by Daniel Carvalho. (
https://gem5-review.googlesource.com/c/public/gem5/+/13697 )
Change subject: mem-cache: Move access latency calculation to Cache
......................................................................
mem-cache: Move access latency calculation to Cache
Access latency was not being calculated properly, as it was
always assuming that for hits reads take as long as writes,
and that parallel accesses would produce the same latency
for read and write misses.
By moving the calculation to the Cache we can use the write/
read information and reduce latency variables duplication.
We assume writes can only be done with sequential tag-data
access.
This patch does not take into account that an access can be
serviced by a pending write from the write buffer, nor does
it take into account lock time for RMW operations. It also
does not properly update the whenReady time of a written
block.
Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <[email protected]>
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache.cc
M src/mem/cache/cache.hh
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/noncoherent_cache.hh
M src/mem/cache/tags/Tags.py
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/base_set_assoc.hh
M src/mem/cache/tags/fa_lru.cc
M src/mem/cache/tags/fa_lru.hh
M src/mem/cache/tags/sector_tags.cc
M src/mem/cache/tags/sector_tags.hh
14 files changed, 175 insertions(+), 108 deletions(-)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Gerrit-Change-Number: 13697
Gerrit-PatchSet: 4
Gerrit-Owner: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-CC: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newpatchset
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