Giacomo Gabrielli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13716
Change subject: config: Extend config scripts to handle Arm SVE
......................................................................
config: Extend config scripts to handle Arm SVE
Change-Id: I64f2f9ff6dc7f2234ef1f05bdb46a55d434f2370
Signed-off-by: Giacomo Gabrielli <[email protected]>
---
M configs/common/FSConfig.py
M configs/common/Options.py
M configs/example/arm/fs_bigLITTLE.py
M configs/example/fs.py
M configs/example/se.py
5 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6747616..e9c0803 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -207,7 +207,7 @@
def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
dtb_filename=None, bare_metal=False, cmdline=None,
external_memory="", ruby=False, security=False,
- ignore_dtb=False):
+ ignore_dtb=False, sve_vl=1):
assert machine_type
default_dtbs = {
@@ -224,6 +224,8 @@
pci_devices = []
+ ArmISA.sve_vl = sve_vl
+
if bare_metal:
self = ArmSystem()
else:
diff --git a/configs/common/Options.py b/configs/common/Options.py
index c36dc38..39beb16 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2013 ARM Limited
+# Copyright (c) 2013, 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -297,6 +297,9 @@
parser.add_option("--arm-iset", default="arm", type="choice",
choices=["arm", "thumb", "aarch64"],
help="ARM instruction set.")
+ parser.add_option("--arm-sve-vl", default="2", type="choice",
+ choices=["1", "2", "4", "8", "16"],
+ help="SVE vector length in quadwords (128-bit)")
def addSEOptions(parser):
diff --git a/configs/example/arm/fs_bigLITTLE.py
b/configs/example/arm/fs_bigLITTLE.py
index 8cf89e3..fcf007d 100644
--- a/configs/example/arm/fs_bigLITTLE.py
+++ b/configs/example/arm/fs_bigLITTLE.py
@@ -113,7 +113,9 @@
super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock,
cpu_voltage, *cpu_config)
-def createSystem(caches, kernel, bootscript, disks=[]):
+def createSystem(caches, kernel, bootscript, sve_vl, disks=[]):
+ ArmISA.sve_vl = sve_vl
+
sys = devices.SimpleSystem(caches, default_mem_size,
kernel=SysPaths.binary(kernel),
readfile=bootscript)
@@ -179,6 +181,9 @@
help="Big CPU clock frequency")
parser.add_argument("--little-cpu-clock", type=str, default="1GHz",
help="Little CPU clock frequency")
+ parser.add_argument("--arm-sve-vl", default=1, type=int,
+ choices=[1, 2, 4, 8, 16],
+ help="SVE vector length in quadwords (128-bit)")
parser.add_argument("--sim-quantum", type=str, default="1ms",
help="Simulation quantum for parallel
simulation. " \
"Default: %(default)s")
@@ -190,6 +195,7 @@
"sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
"Direct parameters of the root object are not accessible, "
"only parameters of its children.")
+
return parser
def build(options):
@@ -214,6 +220,7 @@
system = createSystem(options.caches,
options.kernel,
options.bootscript,
+ options.arm_sve_vl,
disks=disks)
root.system = system
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 3997ed7..6837903 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -98,7 +98,8 @@
external_memory=
options.external_memory_system,
ruby=options.ruby,
-
security=options.enable_security_extensions)
+
security=options.enable_security_extensions,
+ sve_vl=int(options.arm_sve_vl))
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
@@ -238,7 +239,8 @@
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
bm[1], options.dtb_filename,
cmdline=cmdline,
- ignore_dtb=options.generate_dtb)
+ ignore_dtb=options.generate_dtb,
+ sve_vl=options.arm_sve_vl)
# Create a top-level voltage domain
drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
diff --git a/configs/example/se.py b/configs/example/se.py
index f12d4a9..cda2c18 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013, 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -233,6 +233,9 @@
if options.checker:
system.cpu[i].addCheckerCpu()
+ if buildEnv['TARGET_ISA'] == 'arm':
+ ArmISA.sve_vl = int(options.arm_sve_vl)
+
system.cpu[i].createThreads()
if options.ruby:
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I64f2f9ff6dc7f2234ef1f05bdb46a55d434f2370
Gerrit-Change-Number: 13716
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-MessageType: newchange
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