Hello Giacomo Travaglini, Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/14317
to review the following change.
Change subject: cpu-o3: Add a probe to notify memory accesses
......................................................................
cpu-o3: Add a probe to notify memory accesses
Added a probe to the LSQ to allow listening to memory requests.
The probe is named "MemAccess".
Change-Id: I842c5f4f0c5739b1b820c7ede53cb97dd524c32a
---
M src/cpu/o3/iew_impl.hh
M src/cpu/o3/lsq.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/lsq_unit_impl.hh
5 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 8270a71..a64de0c 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -123,8 +123,12 @@
void
DefaultIEW<Impl>::regProbePoints()
{
- ppDispatch = new
ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
- ppMispredict = new
ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
+ ldstQueue.regProbePoints();
+
+ ppDispatch =
+ new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch");
+ ppMispredict =
+ new
ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict");
/**
* Probe point with dynamic instruction as the argument used to probe
when
* an instruction starts to execute.
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 7c78156..0a7e69b 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -81,6 +81,9 @@
/** Registers statistics of each LSQ unit. */
void regStats();
+ /** Registers probes. */
+ void regProbePoints();
+
/** Sets the pointer to the list of active threads. */
void setActiveThreads(std::list<ThreadID> *at_ptr);
@@ -300,6 +303,10 @@
void recvTimingSnoopReq(PacketPtr pkt);
+ /** @return The probe to notify memory accesses */
+ ProbePointArg<PacketPtr> *getMemAccessProbe() const
+ { return ppMemAccess; }
+
/** The CPU pointer. */
O3CPU *cpu;
@@ -329,6 +336,9 @@
/** Number of Threads. */
ThreadID numThreads;
+
+ /** To probe when a memory access is issued */
+ ProbePointArg<PacketPtr> *ppMemAccess;
};
template <class Impl>
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 56b95a5..c443528 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -142,6 +142,14 @@
template<class Impl>
void
+LSQ<Impl>::regProbePoints()
+{
+ ppMemAccess = new ProbePointArg<PacketPtr>(cpu->getProbeManager(),
+ "MemAccess");
+}
+
+template<class Impl>
+void
LSQ<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index f5b60b2..b39f1c2 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -788,6 +788,11 @@
state->mainPkt = data_pkt;
}
+ // Notify listeners that we are issuing a memory request.
+ // Only one notification is sent despite the fact that
+ // two accesses could be generated.
+ lsq->getMemAccessProbe()->notify(data_pkt);
+
// For now, load throughput is constrained by the number of
// load FUs only, and loads do not consume a cache port (only
// stores do).
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index c2750be..97211c4 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1211,6 +1211,7 @@
bool
LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
{
+ lsq->getMemAccessProbe()->notify(data_pkt);
if (!dcachePort->sendTimingReq(data_pkt)) {
// Need to handle becoming blocked on a store.
isStoreBlocked = true;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/14317
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I842c5f4f0c5739b1b820c7ede53cb97dd524c32a
Gerrit-Change-Number: 14317
Gerrit-PatchSet: 1
Gerrit-Owner: Javier Bueno Hedo <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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