Hello Alec Roelke,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/14376
to review the following change.
Change subject: arch-riscv: Fix reset function and style
......................................................................
arch-riscv: Fix reset function and style
In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says that,
on reset:
1. Privilege mode is set to M
2. mstatus.mie <- 0; mstatus.mprv <- 0
3. PC <- reset vector
4. mcause <- reset cause (0 if there is no distinguishing causes)
5. Everything else is undefined
Because of 5, everything else will be left alone
Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
---
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
M src/arch/riscv/interrupts.hh
3 files changed, 41 insertions(+), 51 deletions(-)
diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b5f3d07..5f949b3 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -126,10 +126,12 @@
void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
- if (FullSystem) {
- tc->getCpuPtr()->clearInterrupts(tc->threadId());
- tc->clearArchRegs();
- }
+ tc->setMiscReg(MISCREG_PRV, PRV_M);
+ STATUS status = tc->readMiscReg(MISCREG_STATUS);
+ status.mie = 0;
+ status.mprv = 0;
+ tc->setMiscReg(MISCREG_STATUS, status);
+ tc->setMiscReg(MISCREG_MCAUSE, 0);
// Advance the PC to the implementation-defined reset vector
PCState pc = static_cast<RiscvSystem
*>(tc->getSystemPtr())->resetVect();
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d9cb44c..2176f88 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -95,24 +95,15 @@
class Reset : public FaultBase
{
+ private:
+ const FaultName _name;
- public:
- Reset()
- : _name("reset")
- {}
+ public:
+ Reset() : _name("reset") {}
+ FaultName name() const override { return _name; }
- FaultName
- name() const override
- {
- return _name;
- }
-
- void
- invoke(ThreadContext *tc, const StaticInstPtr &inst =
- StaticInst::nullStaticInstPtr) override;
-
- private:
- const FaultName _name;
+ void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr) override;
};
class InstFault : public RiscvFault
diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh
index 60a5b5b..f593eb6 100644
--- a/src/arch/riscv/interrupts.hh
+++ b/src/arch/riscv/interrupts.hh
@@ -55,36 +55,34 @@
return dynamic_cast<const Params *>(_params);
}
- Interrupts(Params * p) : SimObject(p), cpu(nullptr)
- {}
+ Interrupts(Params * p) : SimObject(p), cpu(nullptr) {}
- void
- setCPU(BaseCPU * _cpu)
- {
- cpu = _cpu;
- }
-
- void
- post(int int_num, int index)
- {
- panic("Interrupts::post not implemented.\n");
- }
-
- void
- clear(int int_num, int index)
- {
- panic("Interrupts::clear not implemented.\n");
- }
-
- void
- clearAll()
- {
- warn_once("Interrupts::clearAll not implemented.\n");
- }
+ void setCPU(BaseCPU * _cpu) { cpu = _cpu; }
bool
checkInterrupts(ThreadContext *tc) const
{
+ return tc->readMiscReg(MISCREG_IP) != 0;
+ }
+
+ Fault
+ getInterrupt(ThreadContext *tc)
+ {
+ assert(checkInterrupts(tc));
+ panic("Interrupts::getInterrupt not implemented.\n");
+ }
+
+ void
+ updateIntrInfo(ThreadContext *tc)
+ {
+ panic("Interrupts::updateIntrInfo not implemented.\n");
+ }
+
+ // Deprecated but still necessary for compatibility
+
+ void
+ post(int int_num, int index)
+ {
warn_once("Interrupts::checkInterrupts just rudimentary
implemented");
/**
* read the machine interrupt register in order to check if
interrupts
@@ -98,17 +96,16 @@
return false;
}
- Fault
- getInterrupt(ThreadContext *tc)
+ void
+ clear(int int_num, int index)
{
- assert(checkInterrupts(tc));
- panic("Interrupts::getInterrupt not implemented.\n");
+ panic("Interrupts::clear not implemented.\n");
}
void
- updateIntrInfo(ThreadContext *tc)
+ clearAll()
{
- panic("Interrupts::updateIntrInfo not implemented.\n");
+ panic("Interrupts::clearAll not implemented.\n");
}
};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Gerrit-Change-Number: 14376
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-MessageType: newchange
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