Alec Roelke has submitted this change and it was merged. ( https://gem5-review.googlesource.com/c/public/gem5/+/14376 )

Change subject: arch-riscv: Fix reset function and style
......................................................................

arch-riscv: Fix reset function and style

In addition to fixing some style issues with resetting, this patch fixes
what happens on reset. The RISC-V privileged ISA reference manual says
that,
on reset:
 1. Privilege mode is set to M
 2. mstatus.mie <- 0; mstatus.mprv <- 0
 3. PC <- reset vector
 4. mcause <- reset cause (0 if there is no distinguishing causes)
 5. Everything else is undefined
Because of 5, everything else will be left alone

Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Reviewed-on: https://gem5-review.googlesource.com/c/14376
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
---
M src/arch/riscv/faults.cc
M src/arch/riscv/faults.hh
2 files changed, 14 insertions(+), 16 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/riscv/faults.cc b/src/arch/riscv/faults.cc
index b5f3d07..a151334 100644
--- a/src/arch/riscv/faults.cc
+++ b/src/arch/riscv/faults.cc
@@ -131,6 +131,13 @@
         tc->clearArchRegs();
     }

+    tc->setMiscReg(MISCREG_PRV, PRV_M);
+    STATUS status = tc->readMiscReg(MISCREG_STATUS);
+    status.mie = 0;
+    status.mprv = 0;
+    tc->setMiscReg(MISCREG_STATUS, status);
+    tc->setMiscReg(MISCREG_MCAUSE, 0);
+
     // Advance the PC to the implementation-defined reset vector
PCState pc = static_cast<RiscvSystem *>(tc->getSystemPtr())->resetVect();
     tc->pcState(pc);
diff --git a/src/arch/riscv/faults.hh b/src/arch/riscv/faults.hh
index d9cb44c..2176f88 100644
--- a/src/arch/riscv/faults.hh
+++ b/src/arch/riscv/faults.hh
@@ -95,24 +95,15 @@

 class Reset : public FaultBase
 {
+  private:
+    const FaultName _name;

-    public:
-        Reset()
-            : _name("reset")
-        {}
+  public:
+    Reset() : _name("reset") {}
+    FaultName name() const override { return _name; }

-        FaultName
-        name() const override
-        {
-            return _name;
-        }
-
-        void
-        invoke(ThreadContext *tc, const StaticInstPtr &inst =
-            StaticInst::nullStaticInstPtr) override;
-
-    private:
-        const FaultName _name;
+    void invoke(ThreadContext *tc, const StaticInstPtr &inst =
+        StaticInst::nullStaticInstPtr) override;
 };

 class InstFault : public RiscvFault

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I81bdf7a88b08874e3c3d5fc6c7f3ca2d796496b8
Gerrit-Change-Number: 14376
Gerrit-PatchSet: 3
Gerrit-Owner: Alec Roelke <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Robert Scheffel <[email protected]>
Gerrit-Reviewer: Tuan Ta <[email protected]>
Gerrit-MessageType: merged
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