Hello Gabe Black, Anthony Gutierrez, Nikos Nikoleris, Giacomo Travaglini,
Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/16522
to look at the new patch set (#3).
Change subject: x86: Call the base class's regStats in X86ISA::TLB
......................................................................
x86: Call the base class's regStats in X86ISA::TLB
When I try to build x86 architecture and run the se.py sample script
with helloworld example, there is a panic warning stated "Not all stats
have been initialized. You may need to add <ParentClass>::regStats() to
a new SimObject's regStats() function."
I see that in x86 tlb.cc, there is no initialization in regStats() function
that causes memory allocation error in some machine which make gem5 exit
abnormally. I add the BaseTLB::regStats(); on TLB::regStats() method and
can solve the problem
Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f
---
M src/arch/x86/tlb.cc
1 file changed, 1 insertion(+), 1 deletion(-)
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I8b62bebc15f896c3136ff4f8253dabbf998f618f
Gerrit-Change-Number: 16522
Gerrit-PatchSet: 3
Gerrit-Owner: Bagus Hanindhito <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Anthony Gutierrez <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-MessageType: newpatchset
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