Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16640
Change subject: arch-power: Add branch target address register instructions
......................................................................
arch-power: Add branch target address register instructions
This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it:
* Move To Target Address Register (mttar)
* Move From Target Address Register (mftar)
* Branch Conditional to Branch Target Address Register (bctar[l])
Change-Id: I5130a22040e30a05e963b1cc8d38abbed9a49edb
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/operands.isa
M src/arch/power/registers.hh
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 3e8f506..2257b8d 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -58,6 +58,7 @@
format BranchRegCondOp {
16: bclr({{ NIA = LR & -4ULL; }}, true, [ IsReturn ]);
528: bcctr({{ NIA = CTR & -4ULL; }});
+ 560: bctar({{ NIA = TAR & -4ULL; }}, true);
}
// Condition register manipulation instructions.
@@ -718,11 +719,13 @@
0x20: mfxer({{ Rt = XER; }});
0x100: mflr({{ Rt = LR; }});
0x120: mfctr({{ Rt = CTR; }});
+ 0x1f9: mftar({{ Rt = TAR; }});
}
467: decode SPR {
0x20: mtxer({{ XER = Rs; }});
0x100: mtlr({{ LR = Rs; }});
0x120: mtctr({{ CTR = Rs; }});
+ 0x1f9: mttar({{ TAR = Rs; }});
}
}
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index c2a45b9..d45cc11 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -65,9 +65,10 @@
# Control registers
'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
+ 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
- 'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
+ 'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
# Setting as IntReg so things are stored as an integer, not double
'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index a494425..a7702ee 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -64,9 +64,9 @@
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
-// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
+// CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR
// and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 9;
+const int NumIntSpecialRegs = 10;
const int NumFloatArchRegs = 32;
const int NumFloatSpecialRegs = 0;
const int NumInternalProcRegs = 0;
@@ -102,6 +102,7 @@
INTREG_XER,
INTREG_LR,
INTREG_CTR,
+ INTREG_TAR,
INTREG_FPSCR,
INTREG_RSV,
INTREG_RSV_LEN,
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I5130a22040e30a05e963b1cc8d38abbed9a49edb
Gerrit-Change-Number: 16640
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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