Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/16642
Change subject: arch-power: Fix remote GDB semantics
......................................................................
arch-power: Fix remote GDB semantics
This fixes the endianness conversions applied to the integer
registers when reading or setting them. This also changes the
registers widths to 64 bits wherever required for compliance
with the 64-bit Power architecture.
The format of the 'g' packet that GDB expects for targets of
type "powerpc:common64" is also fixed by maintaining correct
offsets for the registers and introducing additional padding
to keep the correct packet size.
Change-Id: I7c64c0a2e355a2e5fbab097e9d24c773c475db85
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/remote_gdb.cc
M src/arch/power/remote_gdb.hh
2 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/src/arch/power/remote_gdb.cc b/src/arch/power/remote_gdb.cc
index c8a71c5..d4824c6 100644
--- a/src/arch/power/remote_gdb.cc
+++ b/src/arch/power/remote_gdb.cc
@@ -176,22 +176,23 @@
{
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
- // Default order on 32-bit PowerPC:
- // R0-R31 (32-bit each), F0-F31 (64-bit IEEE754 double),
- // PC, MSR, CR, LR, CTR, XER (32-bit each)
+ // Default order on 64-bit PowerPC:
+ // GPRR0-GPRR31 (64-bit each), FPR0-FPR31 (64-bit IEEE754 double),
+ // CIA, MSR, CR, FPSCR, XER, LR, CTR, TAR
+ // where only CR, FPSCR, XER are 32-bit each and the rest are 64-bit
for (int i = 0; i < NumIntArchRegs; i++)
- r.gpr[i] = htobe((uint32_t)context->readIntReg(i));
+ r.gpr[i] = htog(context->readIntReg(i));
for (int i = 0; i < NumFloatArchRegs; i++)
r.fpr[i] = context->readFloatReg(i);
- r.pc = htobe((uint32_t)context->pcState().pc());
+ r.pc = htog(context->pcState().pc());
r.msr = 0; // Is MSR modeled?
- r.cr = htobe((uint32_t)context->readIntReg(INTREG_CR));
- r.lr = htobe((uint32_t)context->readIntReg(INTREG_LR));
- r.ctr = htobe((uint32_t)context->readIntReg(INTREG_CTR));
- r.xer = htobe((uint32_t)context->readIntReg(INTREG_XER));
+ r.cr = htog((uint32_t)context->readIntReg(INTREG_CR));
+ r.lr = htog(context->readIntReg(INTREG_LR));
+ r.ctr = htog(context->readIntReg(INTREG_CTR));
+ r.xer = htog((uint32_t)context->readIntReg(INTREG_XER));
}
void
@@ -200,17 +201,17 @@
DPRINTF(GDBAcc, "setRegs in remotegdb \n");
for (int i = 0; i < NumIntArchRegs; i++)
- context->setIntReg(i, betoh(r.gpr[i]));
+ context->setIntReg(i, gtoh(r.gpr[i]));
for (int i = 0; i < NumFloatArchRegs; i++)
context->setFloatReg(i, r.fpr[i]);
- context->pcState(betoh(r.pc));
+ context->pcState(gtoh(r.pc));
// Is MSR modeled?
- context->setIntReg(INTREG_CR, betoh(r.cr));
- context->setIntReg(INTREG_LR, betoh(r.lr));
- context->setIntReg(INTREG_CTR, betoh(r.ctr));
- context->setIntReg(INTREG_XER, betoh(r.xer));
+ context->setIntReg(INTREG_CR, gtoh(r.cr));
+ context->setIntReg(INTREG_LR, gtoh(r.lr));
+ context->setIntReg(INTREG_CTR, gtoh(r.ctr));
+ context->setIntReg(INTREG_XER, gtoh(r.xer));
}
BaseGdbRegCache*
diff --git a/src/arch/power/remote_gdb.hh b/src/arch/power/remote_gdb.hh
index 2894fc1..32a3658 100644
--- a/src/arch/power/remote_gdb.hh
+++ b/src/arch/power/remote_gdb.hh
@@ -55,15 +55,19 @@
using BaseGdbRegCache::BaseGdbRegCache;
private:
struct {
- uint32_t gpr[NumIntArchRegs];
+ uint64_t gpr[NumIntArchRegs];
uint64_t fpr[NumFloatArchRegs];
- uint32_t pc;
- uint32_t msr;
+ uint64_t pc;
+ uint64_t msr;
uint32_t cr;
- uint32_t lr;
- uint32_t ctr;
+ uint64_t lr;
+ uint64_t ctr;
uint32_t xer;
- } r;
+
+ /* Remote target is expected to have 174 registers in the 'g'
+ packet with a total size of 1076 bytes */
+ uint8_t __padding[524];
+ } M5_ATTR_PACKED r;
public:
char *data() const { return (char *)&r; }
size_t size() const { return sizeof(r); }
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I7c64c0a2e355a2e5fbab097e9d24c773c475db85
Gerrit-Change-Number: 16642
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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