Hello Gabe Black, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/16648
to look at the new patch set (#2).
Change subject: mem-cache: alias to mem::getMasterPort in TLB class
......................................................................
mem-cache: alias to mem::getMasterPort in TLB class
A recent patch makes the BaseTLB a derived class of MemObject
instead of the generic SimObject.
The BaseTLB::getMasterPort() hides the MemObject method, producing a
compilation error when -Woverloaded-virtual is used.
The TLB:getMasterPort is used to obtain the PageWalkMasterPort if present.
The TLB::getMasterPort() is renamed according to the expected behavior.
Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/generic/tlb.hh
M src/arch/x86/tlb.cc
M src/arch/x86/tlb.hh
M src/cpu/base.cc
6 files changed, 18 insertions(+), 13 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/16648
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Gerrit-Change-Number: 16648
Gerrit-PatchSet: 2
Gerrit-Owner: Andrea Mondelli <[email protected]>
Gerrit-Reviewer: Andrea Mondelli <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-CC: Ivan Pizarro <[email protected]>
Gerrit-MessageType: newpatchset
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