Hi Abhishek, The markDelayed() change fixes the Andrew's issue regarding the assertion: "req == _requests[numTranslatedFragments] || this->isDelayed()".
The other assertion you hit may require a separate fix. Have you tried to comment it out to check if the simulation completes otherwise? Cheers, - Gabor On 22/05/2019, 22:27, "gem5-dev on behalf of Abhishek Singh" <[email protected] on behalf of [email protected]> wrote: Hi Gabor, Your latest change of adding markDelayed() to src/arch/x86/tlb.cc does not solve the problem "gem5.opt: build/X86/mem/packet.hh:1094: T* Packet::getPtr() [with T = unsigned char]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed" Is there any other way, to get gem5 FS x86 with O3CPU working except using AtomicSimpleCPU to create checkpoint and then use O3CPU? As Andrew correctly pointed this problem did not arrive before "LSQ rewrite commit in January:51becd2475748fb5515f261254c48827b3b5c2ba" Best regards, Abhishek On Wed, Mar 20, 2019 at 9:35 AM Gabor Dozsa <[email protected]> wrote: > Hi Andrew, > > There is a fairly lengthy commit message for 51becd2 ("O3 LSQ > Generalisation") which explains briefly the main ideas behind the rewrite. > > Regarding the particular assertion, the reason is likely to be that the > X86 tlb code does not call > 'translation->markDelayed()' when the translation triggers hardware page > walks. Adding markDelayed() to src/arch/x86/tlb.cc should fix the issue. > (You can look at src/arch/arm/tlb.cc for to see how this is done for Arm.) > > Cheers, > - Gabor > > > On 19/03/2019, 19:48, "gem5-dev on behalf of Zigerelli, Andrew D" < > [email protected] on behalf of [email protected]> wrote: > > Dear Giacomo Travaglini, Gabor Dozsa, > > Regarding your LSQ rewrite commit in January: > 51becd2475748fb5515f261254c48827b3b5c2ba > > > Because this is a substantial rewrite, is there any documentation > related to how things work now? > > I'm trying to debug an assert I get with X86 and O3 cpu in lsq_impl.hh. > > LSQ<Impl>::SplitDataRequest::finish(const Fault &fault, const > RequestPtr &req, > ThreadContext* tc, BaseTLB::Mode mode) > _fault.push_back(fault); > assert(req == _requests[numTranslatedFragments] || > this->isDelayed()); > I'm interested in the fix, but I'd also like to know how the new LSQ > works because it's related to my work. > > I can bypass by using the gem5 before the rewrite, but I assume this > is something that should be fixed anyway. > > > Thank you, > > Andrew Zigerelli > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
