Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/17988
to review the following change.
Change subject: arch-arm: Change mcrMrc15TrapToHyp signature
......................................................................
arch-arm: Change mcrMrc15TrapToHyp signature
This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp
helper function. Rather than passing registers as arguments,
we are just passing a ThreadContext pointer
Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
---
M src/arch/arm/insts/misc.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
4 files changed, 26 insertions(+), 32 deletions(-)
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 3f29865..bcb8883 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -339,15 +339,8 @@
Fault
McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
- uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
- uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
- uint32_t scr = xc->readMiscReg(MISCREG_SCR);
- uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
- uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
- uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
+ bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
- hcptr, iss);
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, iss,
EC_TRAPPED_CP15_MCR_MRC);
@@ -371,15 +364,8 @@
Fault
McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData)
const
{
- uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
- uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
- uint32_t scr = xc->readMiscReg(MISCREG_SCR);
- uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
- uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
- uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
+ bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
- hcptr, iss);
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, iss,
EC_TRAPPED_CP15_MCR_MRC);
diff --git a/src/arch/arm/isa/insts/misc.isa
b/src/arch/arm/isa/insts/misc.isa
index 932deeb..92a6b53 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -920,8 +920,9 @@
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
preFlatOp1)).index();
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
- Hcptr, imm);
+
+ bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+
bool can_read, undefined;
std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
// if we're in non secure PL1 mode then we can trap regargless of
whether
@@ -952,8 +953,9 @@
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
preFlatDest)).index();
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
- Hcptr, imm);
+
+ bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
@@ -1092,8 +1094,9 @@
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, preFlatDest)).index();
- bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,
Hstr,
- Hcptr, imm);
+
+ bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr,
Cpsr);
@@ -1190,8 +1193,8 @@
isbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
- if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr,
Scr,
- Hdcr, Hstr, Hcptr, imm)) {
+ if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB,
+ xc->tcBase(), imm)) {
return std::make_shared<HypervisorTrap>(machInst, imm,
EC_TRAPPED_CP15_MCR_MRC);
}
@@ -1206,8 +1209,8 @@
dsbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
- if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr,
Scr,
- Hdcr, Hstr, Hcptr, imm)) {
+ if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB,
+ xc->tcBase(), imm)) {
return std::make_shared<HypervisorTrap>(machInst, imm,
EC_TRAPPED_CP15_MCR_MRC);
}
@@ -1222,8 +1225,8 @@
dmbCode = '''
// If the barrier is due to a CP15 access check for hyp traps
- if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr,
Scr,
- Hdcr, Hstr, Hcptr, imm)) {
+ if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB,
+ xc->tcBase(), imm)) {
return std::make_shared<HypervisorTrap>(machInst, imm,
EC_TRAPPED_CP15_MCR_MRC);
}
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 29b39b8..b41134f 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -461,8 +461,7 @@
}
bool
-mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
- HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
+mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t
iss)
{
bool isRead;
uint32_t crm;
@@ -472,6 +471,12 @@
uint32_t opc2;
bool trapToHype = false;
+ const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+ const HCR hcr = tc->readMiscReg(MISCREG_HCR);
+ const SCR scr = tc->readMiscReg(MISCREG_SCR);
+ const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR);
+ const HSTR hstr = tc->readMiscReg(MISCREG_HSTR);
+ const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index c6ff946..15daeb8 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -313,8 +313,8 @@
}
bool
-mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
- HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
+mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t
iss);
+
bool
mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17988
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae
Gerrit-Change-Number: 17988
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-MessageType: newchange
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