Hello Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/17991
to look at the new patch set (#4).
Change subject: cpu: Add a memory access predicate
......................................................................
cpu: Add a memory access predicate
This changeset introduces a new predicate to guard memory accesses.
The most immediate use for this is to allow proper handling of
predicated-false vector contiguous loads and predicated-false
micro-ops of vector gather loads (added in separate changesets).
Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Signed-off-by: Giacomo Gabrielli <[email protected]>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
8 files changed, 82 insertions(+), 5 deletions(-)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/17991
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Gerrit-Change-Number: 17991
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-CC: Andrea Mondelli <[email protected]>
Gerrit-CC: Anthony Gutierrez <[email protected]>
Gerrit-CC: Daniel Carvalho <[email protected]>
Gerrit-CC: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newpatchset
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