Giacomo Gabrielli has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/17991 )
Change subject: cpu: Add a memory access predicate
......................................................................
cpu: Add a memory access predicate
This changeset introduces a new predicate to guard memory accesses.
The most immediate use for this is to allow proper handling of
predicated-false vector contiguous loads and predicated-false
micro-ops of vector gather loads (added in separate changesets).
Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Signed-off-by: Giacomo Gabrielli <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17991
Tested-by: kokoro <[email protected]>
Reviewed-by: Bradley Wang <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
Maintainer: Nikos Nikoleris <[email protected]>
---
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/checker/cpu.hh
M src/cpu/exec_context.hh
M src/cpu/minor/exec_context.hh
M src/cpu/o3/lsq_unit_impl.hh
M src/cpu/simple/exec_context.hh
M src/cpu/simple_thread.hh
8 files changed, 82 insertions(+), 5 deletions(-)
Approvals:
Nikos Nikoleris: Looks good to me, approved; Looks good to me, approved
Bradley Wang: Looks good to me, but someone else must approve
kokoro: Regressions pass
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index f1c7829..4084241 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -135,6 +135,7 @@
EffAddrValid,
RecordResult,
Predicate,
+ MemAccPredicate,
PredTaken,
IsStrictlyOrdered,
ReqMade,
@@ -851,6 +852,18 @@
}
}
+ bool
+ readMemAccPredicate() const
+ {
+ return instFlags[MemAccPredicate];
+ }
+
+ void
+ setMemAccPredicate(bool val)
+ {
+ instFlags[MemAccPredicate] = val;
+ }
+
/** Sets the ASID. */
void setASID(short addr_space_id) { asid = addr_space_id; }
short getASID() { return asid; }
diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index d8473f7..6d3a3ac 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011, 2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -103,6 +103,7 @@
instFlags.reset();
instFlags[RecordResult] = true;
instFlags[Predicate] = true;
+ instFlags[MemAccPredicate] = true;
lqIdx = -1;
sqIdx = -1;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 7582e5e..8c30000 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, 2016-2017 ARM Limited
+ * Copyright (c) 2011, 2016-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -424,6 +424,18 @@
thread->setPredicate(val);
}
+ bool
+ readMemAccPredicate() const override
+ {
+ return thread->readMemAccPredicate();
+ }
+
+ void
+ setMemAccPredicate(bool val) override
+ {
+ thread->setMemAccPredicate(val);
+ }
+
TheISA::PCState pcState() const override { return thread->pcState(); }
void
pcState(const TheISA::PCState &val) override
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 5909af6..4cad9e3 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014, 2016-2017 ARM Limited
+ * Copyright (c) 2014, 2016-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -316,6 +316,8 @@
virtual bool readPredicate() const = 0;
virtual void setPredicate(bool val) = 0;
+ virtual bool readMemAccPredicate() const = 0;
+ virtual void setMemAccPredicate(bool val) = 0;
/** @} */
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 55391c3..b39bbac 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2014, 2016-2017 ARM Limited
+ * Copyright (c) 2011-2014, 2016-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -319,6 +319,18 @@
thread.setPredicate(val);
}
+ bool
+ readMemAccPredicate() const override
+ {
+ return thread.readMemAccPredicate();
+ }
+
+ void
+ setMemAccPredicate(bool val) override
+ {
+ thread.setMemAccPredicate(val);
+ }
+
TheISA::PCState
pcState() const override
{
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 62402bf..9323e86 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -542,6 +542,16 @@
load_fault = inst->initiateAcc();
+ if (!inst->readMemAccPredicate()) {
+ assert(load_fault == NoFault);
+ assert(inst->readPredicate());
+ inst->setExecuted();
+ inst->completeAcc(nullptr);
+ iewStage->instToCommit(inst);
+ iewStage->activityThisCycle();
+ return NoFault;
+ }
+
if (inst->isTranslationDelayed() && load_fault == NoFault)
return load_fault;
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index fb4ced3..be7a863 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017 ARM Limited
+ * Copyright (c) 2014-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -518,6 +518,18 @@
}
}
+ bool
+ readMemAccPredicate() const override
+ {
+ return thread->readMemAccPredicate();
+ }
+
+ void
+ setMemAccPredicate(bool val) override
+ {
+ thread->setMemAccPredicate(val);
+ }
+
/**
* Invalidate a page in the DTLB <i>and</i> ITLB.
*/
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 733047f..8b5e49a 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -117,6 +117,9 @@
/** Did this instruction execute or is it predicated false */
bool predicate;
+ /** True if the memory access should be skipped for this instruction */
+ bool memAccPredicate;
+
public:
std::string name() const
{
@@ -576,6 +579,18 @@
unsigned readStCondFailures() const override { return
storeCondFailures; }
+ bool
+ readMemAccPredicate()
+ {
+ return memAccPredicate;
+ }
+
+ void
+ setMemAccPredicate(bool val)
+ {
+ memAccPredicate = val;
+ }
+
void
setStCondFailures(unsigned sc_failures) override
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ice6894fe150faec2f2f7ab796a00c99ac843810a
Gerrit-Change-Number: 17991
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Bradley Wang <[email protected]>
Gerrit-Reviewer: Giacomo Gabrielli <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Andrea Mondelli <[email protected]>
Gerrit-CC: Anthony Gutierrez <[email protected]>
Gerrit-CC: Daniel Carvalho <[email protected]>
Gerrit-CC: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: merged
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