Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18389 )
Change subject: arch-arm: Remove un-needed hyp flag in TLBI operations
......................................................................
arch-arm: Remove un-needed hyp flag in TLBI operations
The hyp flag was probably a legacy pre-v8 flag distinguishing
invalidation targeting PL2 translation regime (hyp mode).
Since the introduction of target_el parameter, hyp boolean is not needed
anymore. The patch works by setting the hyp flag in the flush* methods
in the TLB automatically by checking if target_el == EL2.
Change-Id: I798009e09ff24a383dea871e348188bae2685e8e
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.lars...@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanl...@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandb...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389
Maintainer: Andreas Sandberg <andreas.sandb...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
5 files changed, 46 insertions(+), 49 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d5d88e6..654608a 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1191,7 +1191,7 @@
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), false);
+ mbits(newVal, 31,12));
tlbiOp(tc);
return;
@@ -1204,7 +1204,7 @@
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), false);
+ mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
return;
@@ -1220,7 +1220,7 @@
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), true);
+ mbits(newVal, 31,12));
tlbiOp(tc);
return;
@@ -1233,7 +1233,7 @@
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns,
- mbits(newVal, 31,12), true);
+ mbits(newVal, 31,12));
tlbiOp.broadcast(tc);
return;
@@ -1329,7 +1329,7 @@
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, false);
+ TLBIALLN tlbiOp(EL1);
tlbiOp(tc);
return;
}
@@ -1338,7 +1338,7 @@
{
assert32(tc);
- TLBIALLN tlbiOp(EL1, false);
+ TLBIALLN tlbiOp(EL1);
tlbiOp.broadcast(tc);
return;
}
@@ -1347,7 +1347,7 @@
{
assert32(tc);
- TLBIALLN tlbiOp(EL2, true);
+ TLBIALLN tlbiOp(EL2);
tlbiOp(tc);
return;
}
@@ -1356,7 +1356,7 @@
{
assert32(tc);
- TLBIALLN tlbiOp(EL2, true);
+ TLBIALLN tlbiOp(EL2);
tlbiOp.broadcast(tc);
return;
}
@@ -1538,7 +1538,7 @@
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
+ static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp(tc);
return;
@@ -1551,7 +1551,7 @@
scr = readMiscReg(MISCREG_SCR, tc);
TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
- static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
+ static_cast<Addr>(bits(newVal, 43, 0)) << 12);
tlbiOp.broadcast(tc);
return;
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 47c5f96..e54eb25 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2016-2018 ARM Limited
+ * Copyright (c) 2010-2013, 2016-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -265,8 +265,10 @@
}
void
-TLB::flushAllNs(bool hyp, uint8_t target_el, bool ignore_el)
+TLB::flushAllNs(uint8_t target_el, bool ignore_el)
{
+ bool hyp = target_el == EL2;
+
DPRINTF(TLB, "Flushing all NS TLB entries (%s lookup)\n",
(hyp ? "hyp" : "non-hyp"));
int x = 0;
@@ -297,7 +299,7 @@
DPRINTF(TLB, "Flushing TLB entries with mva: %#x, asid: %#x "
"(%s lookup)\n", mva, asn, (secure_lookup ?
"secure" : "non-secure"));
- _flushMva(mva, asn, secure_lookup, false, false, target_el);
+ _flushMva(mva, asn, secure_lookup, false, target_el);
flushTlbMvaAsid++;
}
@@ -326,21 +328,24 @@
}
void
-TLB::flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el)
+TLB::flushMva(Addr mva, bool secure_lookup, uint8_t target_el)
{
DPRINTF(TLB, "Flushing TLB entries with mva: %#x (%s lookup)\n", mva,
(secure_lookup ? "secure" : "non-secure"));
- _flushMva(mva, 0xbeef, secure_lookup, hyp, true, target_el);
+ _flushMva(mva, 0xbeef, secure_lookup, true, target_el);
flushTlbMva++;
}
void
-TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup, bool hyp,
+TLB::_flushMva(Addr mva, uint64_t asn, bool secure_lookup,
bool ignore_asn, uint8_t target_el)
{
TlbEntry *te;
// D5.7.2: Sign-extend address to 64 bits
mva = sext<56>(mva);
+
+ bool hyp = target_el == EL2;
+
te = lookup(mva, asn, vmid, hyp, secure_lookup, false, ignore_asn,
target_el);
while (te != NULL) {
@@ -355,10 +360,10 @@
}
void
-TLB::flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t
target_el)
+TLB::flushIpaVmid(Addr ipa, bool secure_lookup, uint8_t target_el)
{
assert(!isStage2);
- stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, hyp, true, target_el);
+ stage2Tlb->_flushMva(ipa, 0xbeef, secure_lookup, true, target_el);
}
bool
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index fa1b040..fb8d794 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, 2016, 2018 ARM Limited
+ * Copyright (c) 2010-2013, 2016, 2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -254,9 +254,8 @@
/** Remove all entries in the non secure world, depending on whether
they
* were allocated in hyp mode or not
- * @param hyp if the opperation affects hyp mode
*/
- void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
+ void flushAllNs(uint8_t target_el, bool ignore_el = false);
/** Reset the entire TLB. Used for CPU switching to prevent stale
@@ -285,18 +284,16 @@
/** Remove all entries that match the va regardless of asn
* @param mva address to flush from cache
* @param secure_lookup if the operation affects the secure world
- * @param hyp if the operation affects hyp mode
*/
- void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t
target_el);
+ void flushMva(Addr mva, bool secure_lookup, uint8_t target_el);
/**
* Invalidate all entries in the stage 2 TLB that match the given ipa
* and the current VMID
* @param ipa the address to invalidate
* @param secure_lookup if the operation affects the secure world
- * @param hyp if the operation affects hyp mode
*/
- void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t
target_el);
+ void flushIpaVmid(Addr ipa, bool secure_lookup, uint8_t target_el);
Fault trickBoxCheck(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain);
@@ -450,11 +447,10 @@
* @param mva virtual address to flush
* @param asn contextid/asn to flush on match
* @param secure_lookup if the operation affects the secure world
- * @param hyp if the operation affects hyp mode
* @param ignore_asn if the flush should ignore the asn
*/
void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
- bool hyp, bool ignore_asn, uint8_t target_el);
+ bool ignore_asn, uint8_t target_el);
bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool
ignore_el);
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index 64c6ce0..4ff03cc 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -99,26 +99,26 @@
void
TLBIALLN::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushAllNs(hyp, targetEL);
- getDTBPtr(tc)->flushAllNs(hyp, targetEL);
+ getITBPtr(tc)->flushAllNs(targetEL);
+ getDTBPtr(tc)->flushAllNs(targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushAllNs(hyp, targetEL);
- getDTBPtr(checker)->flushAllNs(hyp, targetEL);
+ getITBPtr(checker)->flushAllNs(targetEL);
+ getDTBPtr(checker)->flushAllNs(targetEL);
}
}
void
TLBIMVAA::operator()(ThreadContext* tc)
{
- getITBPtr(tc)->flushMva(addr, secureLookup, hyp, targetEL);
- getDTBPtr(tc)->flushMva(addr, secureLookup, hyp, targetEL);
+ getITBPtr(tc)->flushMva(addr, secureLookup, targetEL);
+ getDTBPtr(tc)->flushMva(addr, secureLookup, targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getITBPtr(checker)->flushMva(addr, secureLookup, hyp, targetEL);
- getDTBPtr(checker)->flushMva(addr, secureLookup, hyp, targetEL);
+ getITBPtr(checker)->flushMva(addr, secureLookup, targetEL);
+ getDTBPtr(checker)->flushMva(addr, secureLookup, targetEL);
}
}
@@ -157,16 +157,16 @@
TLBIIPA::operator()(ThreadContext* tc)
{
getITBPtr(tc)->flushIpaVmid(addr,
- secureLookup, false, targetEL);
+ secureLookup, targetEL);
getDTBPtr(tc)->flushIpaVmid(addr,
- secureLookup, false, targetEL);
+ secureLookup, targetEL);
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
getITBPtr(checker)->flushIpaVmid(addr,
- secureLookup, false, targetEL);
+ secureLookup, targetEL);
getDTBPtr(checker)->flushIpaVmid(addr,
- secureLookup, false, targetEL);
+ secureLookup, targetEL);
}
}
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 05733ab..6bef0f6 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -169,14 +169,11 @@
class TLBIALLN : public TLBIOp
{
public:
- TLBIALLN(ExceptionLevel _targetEL, bool _hyp)
- : TLBIOp(_targetEL, false), hyp(_hyp)
+ TLBIALLN(ExceptionLevel _targetEL)
+ : TLBIOp(_targetEL, false)
{}
void operator()(ThreadContext* tc) override;
-
- protected:
- bool hyp;
};
/** TLB Invalidate by VA, All ASID */
@@ -184,15 +181,14 @@
{
public:
TLBIMVAA(ExceptionLevel _targetEL, bool _secure,
- Addr _addr, bool _hyp)
- : TLBIOp(_targetEL, _secure), addr(_addr), hyp(_hyp)
+ Addr _addr)
+ : TLBIOp(_targetEL, _secure), addr(_addr)
{}
void operator()(ThreadContext* tc) override;
protected:
Addr addr;
- bool hyp;
};
/** TLB Invalidate by VA */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18389
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I798009e09ff24a383dea871e348188bae2685e8e
Gerrit-Change-Number: 18389
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Anouk Van Laer <anouk.vanl...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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