Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18488 )
Change subject: arch: Stop using TheISA within the ISAs.
......................................................................
arch: Stop using TheISA within the ISAs.
We know for sure what the ISA is, so there's no need for the
indirection.
Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/alpha/utility.cc
M src/arch/arm/isa/insts/fp64.isa
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/insts/neon64_mem.isa
M src/arch/arm/isa/insts/sve.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/tracers/tarmac_base.cc
M src/arch/arm/tracers/tarmac_base.hh
M src/arch/arm/tracers/tarmac_parser.cc
M src/arch/arm/tracers/tarmac_parser.hh
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/tracers/tarmac_record_v8.hh
M src/arch/arm/tracers/tarmac_tracer.cc
M src/arch/arm/tracers/tarmac_tracer.hh
M src/arch/mips/utility.cc
M src/arch/power/stacktrace.hh
M src/arch/riscv/stacktrace.hh
M src/arch/sparc/utility.cc
M src/arch/x86/process.cc
20 files changed, 58 insertions(+), 62 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
Brandon Potter: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/alpha/utility.cc b/src/arch/alpha/utility.cc
index c03e7b0..c644911 100644
--- a/src/arch/alpha/utility.cc
+++ b/src/arch/alpha/utility.cc
@@ -100,7 +100,7 @@
void
skipFunction(ThreadContext *tc)
{
- TheISA::PCState newPC = tc->pcState();
+ PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}
diff --git a/src/arch/arm/isa/insts/fp64.isa
b/src/arch/arm/isa/insts/fp64.isa
index 26803e7..7decbac 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -45,7 +45,7 @@
exec_output = ""
zeroSveVecRegUpperPartCode = '''
- TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/insts/ldr64.isa
b/src/arch/arm/isa/insts/ldr64.isa
index fe7eaf0..56112a7 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -185,7 +185,7 @@
accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
elif self.flavor == "fp":
accEpilogCode = '''
- TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+ ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmStaticInst::getCurSveVecLen<uint64_t>(
xc->tcBase()));
'''
@@ -239,10 +239,10 @@
# Code that actually handles the access
if self.flavor == "fp":
accEpilogCode = '''
- TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+ ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
ArmStaticInst::getCurSveVecLen<uint64_t>(
xc->tcBase()));
- TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
+ ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
ArmStaticInst::getCurSveVecLen<uint64_t>(
xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa
b/src/arch/arm/isa/insts/neon64_mem.isa
index 8f53369..03ad294 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -45,7 +45,7 @@
exec_output = ''
zeroSveVecRegUpperPartCode = '''
- TheISA::ISA::zeroSveVecRegUpperPart(%s,
+ ArmISA::ISA::zeroSveVecRegUpperPart(%s,
ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
'''
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index e5e9e24..c46a34d 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1555,7 +1555,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -1616,7 +1616,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto tmpVec = tmpVecC.as<Element>();
int ePow2Count = 1;
while (ePow2Count < eCount) {
@@ -1761,7 +1761,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxOp2 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
auxOp2[i] = AA64FpOp2_ud[i];
@@ -1917,7 +1917,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
auxGpOp[i] = GpOp_x[i];
@@ -1981,7 +1981,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
tmpPred[i] = GpOp_x[i];
@@ -2140,7 +2140,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
tmpPred[i] = GpOp_x[i];
@@ -2185,7 +2185,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto tmpPred = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
tmpPred[i] = GpOp_x[i];
@@ -2268,7 +2268,7 @@
unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
xc->tcBase());
bool dobreak = false;
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount; ++i) {
auxGpOp[i] = GpOp_ub[i];
@@ -2320,7 +2320,7 @@
unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
xc->tcBase());
bool last = POp1_ub.lastActive(GpOp_ub, eCount);
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount; ++i) {
auxGpOp[i] = GpOp_ub[i];
@@ -2458,7 +2458,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxGpOp[i] = GpOp_x[i];
@@ -2500,7 +2500,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxGpOp = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i)
auxGpOp[i] = GpOp_x[i];
@@ -2568,14 +2568,14 @@
if unpackHalf == Unpack.Low:
if regType == SrcRegType.Predicate:
code += '''
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxPOp1 = tmpPredC.as<SElement>();
for (int i = 0; i < eCount; ++i) {
auxPOp1[i] = POp1_xs[i];
}'''
else:
code += '''
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<SElement>();
for (int i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_xs[i];
@@ -2636,7 +2636,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -2707,7 +2707,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxOp1 = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -2736,7 +2736,7 @@
code = sveEnabledCheckCode + '''
unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
xc->tcBase());
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
int firstelem = -1, lastelem = -2;
for (int i = 0; i < eCount; ++i) {
@@ -2799,7 +2799,7 @@
xc->tcBase());'''
if srcType == SrcRegType.Predicate:
code += '''
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxPOp1 = tmpPredC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
uint8_t v = POp1_x.get_raw(i);
@@ -2808,7 +2808,7 @@
PDest_x[0] = 0;'''
else:
code += '''
- TheISA::VecRegContainer tmpRegC;
+ ArmISA::VecRegContainer tmpRegC;
auto auxOp1 = tmpRegC.as<Element>();
for (unsigned i = 0; i < eCount; ++i) {
auxOp1[i] = AA64FpOp1_x[i];
@@ -4464,7 +4464,7 @@
constexpr unsigned sz = sizeof(Element);
int s;
int part = %d;
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxPDest = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = 2 * i + part;
@@ -4485,7 +4485,7 @@
trnIterCode = '''
int s;
int part = %d;
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = 2 * i + part;
@@ -4681,7 +4681,7 @@
constexpr unsigned sz = sizeof(Element);
int s;
int part = %d;
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxPDest = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount; i++) {
s = 2 * i + part;
@@ -4705,7 +4705,7 @@
uzpIterCode = '''
int s;
int part = %d;
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount; i++) {
s = 2 * i + part;
@@ -4766,7 +4766,7 @@
constexpr unsigned sz = sizeof(Element);
int s;
int part = %d;
- TheISA::VecPredRegContainer tmpPredC;
+ ArmISA::VecPredRegContainer tmpPredC;
auto auxPDest = tmpPredC.as<uint8_t>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = i + (part * (eCount / 2));
@@ -4787,7 +4787,7 @@
zipIterCode = '''
int s;
int part = %d;
- TheISA::VecRegContainer tmpVecC;
+ ArmISA::VecRegContainer tmpVecC;
auto auxDest = tmpVecC.as<Element>();
for (unsigned i = 0; i < eCount / 2; i++) {
s = i + (part * (eCount / 2));
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f656da..0a0469a 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -51,12 +51,12 @@
'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
- 'vc' : 'TheISA::VecRegContainer',
+ 'vc' : 'ArmISA::VecRegContainer',
# For operations that are implemented as a template
'x' : 'TPElem',
'xs' : 'TPSElem',
'xd' : 'TPDElem',
- 'pc' : 'TheISA::VecPredRegContainer',
+ 'pc' : 'ArmISA::VecPredRegContainer',
'pb' : 'uint8_t'
}};
diff --git a/src/arch/arm/tracers/tarmac_base.cc
b/src/arch/arm/tracers/tarmac_base.cc
index 79e951a..3b6201d 100644
--- a/src/arch/arm/tracers/tarmac_base.cc
+++ b/src/arch/arm/tracers/tarmac_base.cc
@@ -47,7 +47,7 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-using namespace TheISA;
+using namespace ArmISA;
namespace Trace {
diff --git a/src/arch/arm/tracers/tarmac_base.hh
b/src/arch/arm/tracers/tarmac_base.hh
index 7dab87b..4e6cbe0 100644
--- a/src/arch/arm/tracers/tarmac_base.hh
+++ b/src/arch/arm/tracers/tarmac_base.hh
@@ -85,7 +85,7 @@
{
InstEntry() = default;
InstEntry(ThreadContext* thread,
- TheISA::PCState pc,
+ ArmISA::PCState pc,
const StaticInstPtr staticInst,
bool predicate);
@@ -101,7 +101,7 @@
struct RegEntry
{
RegEntry() = default;
- RegEntry(TheISA::PCState pc);
+ RegEntry(ArmISA::PCState pc);
RegType type;
RegIndex index;
@@ -123,7 +123,7 @@
public:
TarmacBaseRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState _pc,
+ const StaticInstPtr _staticInst, ArmISA::PCState _pc,
const StaticInstPtr _macroStaticInst = NULL);
virtual void dump() = 0;
@@ -135,7 +135,7 @@
* @param pc program counter (PCState) variable
* @return Instruction Set State for the given PCState
*/
- static ISetState pcToISetState(TheISA::PCState pc);
+ static ISetState pcToISetState(ArmISA::PCState pc);
};
diff --git a/src/arch/arm/tracers/tarmac_parser.cc
b/src/arch/arm/tracers/tarmac_parser.cc
index 860bb1b..04a2a05 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -57,7 +57,7 @@
#include "sim/sim_exit.hh"
using namespace std;
-using namespace TheISA;
+using namespace ArmISA;
namespace Trace {
@@ -743,7 +743,7 @@
void
TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
- TheISA::PCState pc)
+ ArmISA::PCState pc)
{
ostream &outs = Trace::output();
outs << "\nMismatch between gem5 and TARMAC trace @ " << dec <<
curTick()
@@ -776,8 +776,8 @@
// By default TARMAC splits memory accesses into 4-byte chunks (see
// 'loadstore-display-width' option in TARMAC plugin)
uint32_t written_data = 0;
- unsigned mem_flags = TheISA::TLB::MustBeOne | 3 |
- TheISA::TLB::AllowUnaligned;
+ unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 |
+ ArmISA::TLB::AllowUnaligned;
ISetState isetstate;
@@ -1051,7 +1051,7 @@
unsigned flags)
{
const RequestPtr &req = memReq;
- TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+ ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
req->setVirt(0, addr, size, flags, thread->pcState().instAddr(),
Request::funcMasterId);
diff --git a/src/arch/arm/tracers/tarmac_parser.hh
b/src/arch/arm/tracers/tarmac_parser.hh
index 6acdd62..afba50f 100644
--- a/src/arch/arm/tracers/tarmac_parser.hh
+++ b/src/arch/arm/tracers/tarmac_parser.hh
@@ -83,7 +83,7 @@
/** Current instruction. */
const StaticInstPtr inst;
/** PC of the current instruction. */
- TheISA::PCState pc;
+ ArmISA::PCState pc;
/** True if a mismatch has been detected for this instruction. */
bool mismatch;
/**
@@ -95,7 +95,7 @@
TarmacParserRecordEvent(TarmacParser& _parent,
ThreadContext *_thread,
const StaticInstPtr _inst,
- TheISA::PCState _pc,
+ ArmISA::PCState _pc,
bool _mismatch,
bool _mismatch_on_pc_or_opcode) :
parent(_parent), thread(_thread), inst(_inst), pc(_pc),
@@ -130,10 +130,10 @@
* by gem5.
*/
static void printMismatchHeader(const StaticInstPtr inst,
- TheISA::PCState pc);
+ ArmISA::PCState pc);
TarmacParserRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState
_pc,
+ const StaticInstPtr _staticInst, ArmISA::PCState
_pc,
TarmacParser& _parent,
const StaticInstPtr _macroStaticInst = NULL);
@@ -241,7 +241,7 @@
InstRecord *
getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr
staticInst,
- TheISA::PCState pc,
+ ArmISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL)
{
if (!started && pc.pc() == startPc)
diff --git a/src/arch/arm/tracers/tarmac_record.hh
b/src/arch/arm/tracers/tarmac_record.hh
index f54abf5..d253473 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -178,7 +178,7 @@
public:
TarmacTracerRecord(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState
_pc,
+ const StaticInstPtr _staticInst, ArmISA::PCState
_pc,
TarmacTracer& _tracer,
const StaticInstPtr _macroStaticInst = NULL);
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc
b/src/arch/arm/tracers/tarmac_record_v8.cc
index dea0409..90f1a6f 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -56,7 +56,7 @@
const auto thread = tarmCtx.thread;
// Evaluate physical address
- TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+ ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
paddrValid = dtb->translateFunctional(thread, addr, paddr);
}
@@ -70,7 +70,7 @@
const auto thread = tarmCtx.thread;
// Evaluate physical address
- TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+ ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
dtb->translateFunctional(thread, addr, paddr);
}
diff --git a/src/arch/arm/tracers/tarmac_record_v8.hh
b/src/arch/arm/tracers/tarmac_record_v8.hh
index adf638f..a727ea6 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.hh
+++ b/src/arch/arm/tracers/tarmac_record_v8.hh
@@ -130,7 +130,7 @@
public:
TarmacTracerRecordV8(Tick _when, ThreadContext *_thread,
- const StaticInstPtr _staticInst, TheISA::PCState
_pc,
+ const StaticInstPtr _staticInst, ArmISA::PCState
_pc,
TarmacTracer& _parent,
const StaticInstPtr _macroStaticInst = NULL)
: TarmacTracerRecord(_when, _thread, _staticInst, _pc,
diff --git a/src/arch/arm/tracers/tarmac_tracer.cc
b/src/arch/arm/tracers/tarmac_tracer.cc
index b6f876d..41e4e49 100644
--- a/src/arch/arm/tracers/tarmac_tracer.cc
+++ b/src/arch/arm/tracers/tarmac_tracer.cc
@@ -75,7 +75,7 @@
InstRecord *
TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst,
- TheISA::PCState pc,
+ ArmISA::PCState pc,
const StaticInstPtr macroStaticInst)
{
// Check if we need to start tracing since we have passed the
diff --git a/src/arch/arm/tracers/tarmac_tracer.hh
b/src/arch/arm/tracers/tarmac_tracer.hh
index 7873999..58a47d1 100644
--- a/src/arch/arm/tracers/tarmac_tracer.hh
+++ b/src/arch/arm/tracers/tarmac_tracer.hh
@@ -63,7 +63,7 @@
public:
TarmacContext(ThreadContext* _thread,
const StaticInstPtr _staticInst,
- TheISA::PCState _pc)
+ ArmISA::PCState _pc)
: thread(_thread), staticInst(_staticInst), pc(_pc)
{}
@@ -72,7 +72,7 @@
public:
ThreadContext* thread;
const StaticInstPtr staticInst;
- TheISA::PCState pc;
+ ArmISA::PCState pc;
};
/**
@@ -99,7 +99,7 @@
*/
InstRecord* getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst,
- TheISA::PCState pc,
+ ArmISA::PCState pc,
const StaticInstPtr macroStaticInst = NULL);
protected:
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index bb20c4c..495845d 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -268,7 +268,7 @@
void
skipFunction(ThreadContext *tc)
{
- TheISA::PCState newPC = tc->pcState();
+ PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}
diff --git a/src/arch/power/stacktrace.hh b/src/arch/power/stacktrace.hh
index aec9183..093c649 100644
--- a/src/arch/power/stacktrace.hh
+++ b/src/arch/power/stacktrace.hh
@@ -57,8 +57,6 @@
class StackTrace
{
- protected:
- typedef TheISA::MachInst MachInst;
private:
ThreadContext *tc;
std::vector<Addr> stack;
diff --git a/src/arch/riscv/stacktrace.hh b/src/arch/riscv/stacktrace.hh
index f146ca8..62f9a47 100644
--- a/src/arch/riscv/stacktrace.hh
+++ b/src/arch/riscv/stacktrace.hh
@@ -57,8 +57,6 @@
class StackTrace
{
- protected:
- typedef TheISA::MachInst MachInst;
private:
ThreadContext *tc;
std::vector<Addr> stack;
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 8b0b4ab..6b3e5d2 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -248,7 +248,7 @@
void
skipFunction(ThreadContext *tc)
{
- TheISA::PCState newPC = tc->pcState();
+ PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg));
tc->pcState(newPC);
}
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index d01afbc..f4469bd 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -150,7 +150,7 @@
void
I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
{
- TheISA::PCState pc = tc->pcState();
+ PCState pc = tc->pcState();
Addr eip = pc.pc();
if (eip >= vsyscallPage.base &&
eip < vsyscallPage.base + vsyscallPage.size) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Gerrit-Change-Number: 18488
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Brandon Potter <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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