Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/18549
Change subject: arm: Add a virtual misc register for accessing the SVE
vector length.
......................................................................
arm: Add a virtual misc register for accessing the SVE vector length.
This avoids having to use the special accessor function, since the ISA
object already knows how to serve up integer values through other
common interfaces.
Change-Id: I120c0b10b36999b1e025bb021be83066f9c2fa9b
---
M src/arch/arm/isa.cc
M src/arch/arm/miscregs.hh
2 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 654608a..9587b56 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -722,6 +722,9 @@
case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
+ case MISCREG_SVE_VEC_LEN_BITS:
+ return getCurSveVecLenInBits(tc);
+
default:
break;
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index feef79e..1290e5d 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -905,6 +905,9 @@
// saving/restoring register values.
NUM_PHYS_MISCREGS,
+ // "Register" for retrieving the current SVE vector length in bits.
+ MISCREG_SVE_VEC_LEN_BITS,
+
// Dummy registers
MISCREG_NOP,
MISCREG_RAZ,
@@ -1837,6 +1840,7 @@
"num_phys_regs",
// Dummy registers
+ "sve_vec_len_bits",
"nop",
"raz",
"cp14_unimpl",
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I120c0b10b36999b1e025bb021be83066f9c2fa9b
Gerrit-Change-Number: 18549
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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