Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/19228 )
Change subject: arch-arm: Move the memacc_code before op_wb in fp loads
......................................................................
arch-arm: Move the memacc_code before op_wb in fp loads
This is trying to fix the bug that arises when a memory exception
is generated during a fp flavoured load (A memory load targeting
a SIMD & FP register).
With the previous template a fault was not stopping the register
value to be modified (wrong)
if (fault == NoFault) {
fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
The patch introduces a Load64FpExecute template which is moving the
register write (memacc_code) just before the op_wb
Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-by: Nikos Nikoleris <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19228
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/isa/insts/ldr64.isa
M src/arch/arm/isa/templates/mem64.isa
2 files changed, 32 insertions(+), 1 deletion(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/ldr64.isa
b/src/arch/arm/isa/insts/ldr64.isa
index 56112a7..801316e 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -99,6 +99,13 @@
if self.flavor in ("acex", "exclusive", "exp", "acexp"):
self.memFlags.append("Request::LLSC")
+ # Using a different execute template for fp flavoured loads.
+ # In this specific template the memacc_code is executed
+ # conditionally depending of wether the memory load has
+ # generated any fault
+ if flavor == "fp":
+ self.fullExecTemplate = eval(self.execBase + 'FpExecute')
+
def buildEACode(self):
# Address computation code
eaCode = ""
diff --git a/src/arch/arm/isa/templates/mem64.isa
b/src/arch/arm/isa/templates/mem64.isa
index bb8594c..fd79669 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2011-2014, 2017 ARM Limited
+// Copyright (c) 2011-2014, 2017, 2019 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -70,6 +70,30 @@
}
}};
+def template Load64FpExecute {{
+ Fault %(class_name)s::execute(ExecContext *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Addr EA;
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+ %(op_rd)s;
+ %(ea_code)s;
+
+ if (fault == NoFault) {
+ fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
+ }
+
+ if (fault == NoFault) {
+ %(memacc_code)s;
+ %(op_wb)s;
+ }
+
+ return fault;
+ }
+}};
+
def template Store64Execute {{
Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I1c89c525dfa7a4ef489abe0872cd7baacdd6ce3c
Gerrit-Change-Number: 19228
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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