Hi ARM folks. I'm trying to implement checkpointing for the fast model CPUs, and to do that I need to understand the mapping between the official, architectural name of various registers and the storage gem5 uses. I see this documentation online:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0801a/CJAHDGCF.html which suggests that there are 32 128 bit (16 byte) registers called either Q0-31 or V0-31 (these map to the same thing), which is the same as having 128 32 bit floating point registers. I see in the ARM register constant definitions that there are 128 single precision floating point registers for v8 which makes sense, but what are the "special" registers for beyond that? Also, the documentation online seems to suggest that the SIMD (ie vector) registers are the same thing as these floating point registers. Why then is there a set of vector registers which are separate from the floating point registers? Is there another set of registers defined by the ISA which are distinct, or is this a bug? Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
