Ok, I think that's mostly true, but in investigating this further I think I found two bugs in the ARM implementation. I do see that the ARM KVM CPU uses readFloatRegFlat to transfer VFP state back and forth, and this will obviously not work if the state isn't actually stored in the FP register file.
Also I also see that in macromem.cc, some of the MicroLdrNeon1Uop instructions are being fed a index called ufp0 (which I think originally meant microcode FP register 0) which is set to NumFloatV7ArchRegs. When only V7 was supported that would have been beyond the architecturally indexable registers, and so was free to use as a microcode register. Now that there are a bunch of other registers there which are accessible in v8, that means this scratch register actually lies on top of a random floating point register simulated code *can* see, corrupting data. Gabe On Mon, Nov 4, 2019 at 1:28 AM Giacomo Travaglini < [email protected]> wrote: > Hi Gabe, > > I am not sure why the vector registers were added as a separate storage. > When they were introduced, all AA64 Floating point operations were using > them (+SIMD): > > VecRegContainer vecRegs[TheISA::NumVecRegs]; > > while AA32 was still using floating point registers. > > RegVal floatRegs[TheISA::NumFloatRegs]; > > This was definitely a bug and it was fixed by: > > https://gem5-review.googlesource.com/c/public/gem5/+/15603 > > At this point I can say ARM is not using the floatRegs storage anymore, and > it is using vecRegs for FP&SIMD operations. > > > Giacomo > ________________________________ > From: gem5-dev <[email protected]> on behalf of Gabe Black < > [email protected]> > Sent: 01 November 2019 23:40 > To: gem5 Developer List <[email protected]> > Subject: [gem5-dev] floating point vs vector registers in ARM > > Hi ARM folks. I'm trying to implement checkpointing for the fast model > CPUs, and to do that I need to understand the mapping between the official, > architectural name of various registers and the storage gem5 uses. I see > this documentation online: > > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0801a/CJAHDGCF.html > > which suggests that there are 32 128 bit (16 byte) registers called either > Q0-31 or V0-31 (these map to the same thing), which is the same as having > 128 32 bit floating point registers. > > I see in the ARM register constant definitions that there are 128 single > precision floating point registers for v8 which makes sense, but what are > the "special" registers for beyond that? > > Also, the documentation online seems to suggest that the SIMD (ie vector) > registers are the same thing as these floating point registers. Why then is > there a set of vector registers which are separate from the floating point > registers? Is there another set of registers defined by the ISA which are > distinct, or is this a bug? > > Gabe > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
