Hi Gabe, VecPredRegs are Predicate registers. Those are registers used in the ARM Scalable Vector Extension (SVE):
https://static.docs.arm.com/ddi0584/a/DDI0584A_a_SVE_supp_armv8A.pdf ARM Architecture Reference Manual Supplement<https://static.docs.arm.com/ddi0584/a/DDI0584A_a_SVE_supp_armv8A.pdf> ARM Architecture Reference Manual Supplement ... arm® arm® ... static.docs.arm.com Could you point me to the Fast Models documentation you are using ? P.S. I am not sure about what FM allows you to do, but consider that in real life the CortexA76 doesn't provide SVE support. ________________________________ From: gem5-dev <[email protected]> on behalf of Gabe Black <[email protected]> Sent: 04 November 2019 23:55 To: gem5 Developer List <[email protected]> Subject: [gem5-dev] VecPredReg architectural equivalent? Hi ARM folks. Could you please tell me what the architectural equivalent of the VecPredRegs are? I need to know what to put in the checkpoint for them. I don't see anything in the list of "resources" (mostly registers) that fast models provide that looks like it's a match. Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
