Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/23524 )
Change subject: arch-arm: Avoid creating an empty byteEnable vector
......................................................................
arch-arm: Avoid creating an empty byteEnable vector
This behaviour will be forbidden in following patches.
Instead, create an all true vector.
JIRA: https://gem5.atlassian.net/browse/GEM5-196
Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23524
Reviewed-by: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/arm/isa/insts/sve_mem.isa
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Giacomo Travaglini: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa/insts/sve_mem.isa
b/src/arch/arm/isa/insts/sve_mem.isa
index dd3d582..b36c1b2 100644
--- a/src/arch/arm/isa/insts/sve_mem.isa
+++ b/src/arch/arm/isa/insts/sve_mem.isa
@@ -774,7 +774,7 @@
EA = XBase + ((int64_t) imm * %(memacc_size)s)''' % {
'memacc_size': 'eCount / 8' if isPred else 'eCount'}
loadRdEnableCode = '''
- auto rdEn = std::vector<bool>();
+ auto rdEn = std::vector<bool>(memAccessSize, true);
'''
if isPred:
loadMemAccCode = '''
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I61d2852610281f2d7c7a669dcb4d2728be194f52
Gerrit-Change-Number: 23524
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Ciro Santilli <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Nikos Nikoleris <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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